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Searched refs:ANA_REG9_PLLLSEL_1_6M (Results 1 – 5 of 5) sorted by relevance

/bsp/Vango/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/
A Dlib_clk.h95 #define ANA_REG9_PLLLSEL_1_6M (0x4U << ANA_REG9_PLLLSEL_Pos) macro
149 #define CLK_PLLL_1_6384MHz ANA_REG9_PLLLSEL_1_6M
/bsp/Vango/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/
A Dlib_clk.c494 case ANA_REG9_PLLLSEL_1_6M: in CLK_GetHCLKFreq()
555 case ANA_REG9_PLLLSEL_1_6M: in CLK_GetPLLLFreq()
/bsp/Vango/v85xx/Libraries/VangoV85xx_standard_peripheral/Include/
A Dlib_clk.h120 #define CLK_PLLL_1_6384MHz ANA_REG9_PLLLSEL_1_6M
/bsp/Vango/v85xx/Libraries/VangoV85xx_standard_peripheral/Source/
A Dlib_clk.c509 case ANA_REG9_PLLLSEL_1_6M: in CLK_GetHCLKFreq()
/bsp/Vango/v85xx/Libraries/CMSIS/Vango/V85xx/Include/
A Dtarget.h1051 #define ANA_REG9_PLLLSEL_1_6M (0x4U << ANA_REG9_PLLLSEL_Pos) macro

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