Searched refs:ANA_REG9_PLLLSEL_1_6M (Results 1 – 5 of 5) sorted by relevance
95 #define ANA_REG9_PLLLSEL_1_6M (0x4U << ANA_REG9_PLLLSEL_Pos) macro149 #define CLK_PLLL_1_6384MHz ANA_REG9_PLLLSEL_1_6M
494 case ANA_REG9_PLLLSEL_1_6M: in CLK_GetHCLKFreq()555 case ANA_REG9_PLLLSEL_1_6M: in CLK_GetPLLLFreq()
120 #define CLK_PLLL_1_6384MHz ANA_REG9_PLLLSEL_1_6M
509 case ANA_REG9_PLLLSEL_1_6M: in CLK_GetHCLKFreq()
1051 #define ANA_REG9_PLLLSEL_1_6M (0x4U << ANA_REG9_PLLLSEL_Pos) macro
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