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Searched refs:AP_RW (Results 1 – 6 of 6) sorted by relevance

/bsp/raspberry-pi/raspi3-32/cpu/
A Dmmu.h13 #define AP_RW (3 << 10) //supervisor=RW, user=RW macro
31 #define RW_CB (AP_RW | DOMAIN0 | CB | DESC_SEC)
33 #define RW_CNB (AP_RW | DOMAIN0 | CNB | DESC_SEC)
35 #define RW_NCNB (AP_RW | DOMAIN0 | NCNB | DESC_SEC)
37 #define RW_NCNBXN (AP_RW | DOMAIN0 | NCNB | DESC_SEC | XN)
39 #define RW_FAULT (AP_RW | DOMAIN1 | NCNB | DESC_SEC)
44 #define NORMAL_MEM (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC)
/bsp/allwinner_tina/libcpu/
A Dmmu.h22 #define AP_RW (3<<10) //supervisor=RW, user=RW macro
34 #define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */
35 #define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */
36 #define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
37 #define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
/bsp/raspberry-pi/raspi2/cpu/
A Dmmu.c22 #define AP_RW (3<<10) //supervisor=RW, user=RW macro
36 #define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
38 #define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
40 #define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
42 #define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
44 #define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
/bsp/nxp/imx/imx6sx/cortex-a9/cpu/
A Dmmu.c22 #define AP_RW (3<<10) //supervisor=RW, user=RW macro
36 #define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
38 #define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
40 #define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
42 #define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
44 #define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
/bsp/ft2004/drivers/
A Dboard.c28 #define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWT | DESC_SEC)
/bsp/nuvoton/libraries/ma35/rtt_port/
A Ddrv_common_aarch32.c33 #define NORMAL_MEM_UNCACHED (SHARED|AP_RW|DOMAIN0|STRONGORDER|DESC_SEC)

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