Searched refs:AT91_PMC (Results 1 – 3 of 3) sorted by relevance
18 #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */19 #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */21 #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */53 #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */57 #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */58 #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */69 #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */112 #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */113 #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */114 #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */[all …]
110 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) macro
858 at91_sys_write(AT91_PMC + AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); //enable macb clock in rt_hw_macb_init()
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