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Searched refs:ATTR_ALIGN (Results 1 – 5 of 5) sorted by relevance

/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_common.h209 #define ATTR_ALIGN(alignment) __attribute__((aligned(alignment))) macro
216 ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment)
220 ATTR_PLACE_AT_NONCACHEABLE ATTR_ALIGN(alignment)
224 ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_ALIGN(alignment)
229 ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_ALIGN(alignment)
234 ATTR_PLACE_AT_FAST_RAM ATTR_ALIGN(alignment)
238 ATTR_PLACE_AT_FAST_RAM_BSS ATTR_ALIGN(alignment)
242 ATTR_PLACE_AT_FAST_RAM_INIT ATTR_ALIGN(alignment)
246 ATTR_RAMFUNC ATTR_ALIGN(alignment)
/bsp/hpmicro/libraries/drivers/
A Ddrv_i2s.c60 ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s0_tx_buff[I2S_FIFO_SIZE];
61 ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s0_rx_buff[I2S_FIFO_SIZE];
64 ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s1_tx_buff[I2S_FIFO_SIZE];
65 ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s1_rx_buff[I2S_FIFO_SIZE];
68 ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s2_tx_buff[I2S_FIFO_SIZE];
69 ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s2_rx_buff[I2S_FIFO_SIZE];
72 ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s3_tx_buff[I2S_FIFO_SIZE];
73 ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s3_rx_buff[I2S_FIFO_SIZE];
A Ddrv_pdm.c302 ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t pdm_rx_fifo[PDM_FIFO_SIZE]; in ATTR_ALIGN() function
A Ddrv_dao.c300 ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t dao_tx_fifo[DAO_FIFO_SIZE]; in ATTR_ALIGN() function
A Ddrv_uart_v2.c62 ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t rx_idle_tmp_buffer[1024];

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