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Searched refs:BASE (Results 1 – 25 of 78) sorted by relevance

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/bsp/raspberry-pi/raspi4-64/drivers/
A Ddrv_uart.h59 #define PL011_REG_DR(BASE) HWREG32(BASE + 0x00) argument
60 #define PL011_REG_RSRECR(BASE) HWREG32(BASE + 0x04) argument
61 #define PL011_REG_RESERVED0(BASE) HWREG32(BASE + 0x08) argument
62 #define PL011_REG_FR(BASE) HWREG32(BASE + 0x18) argument
63 #define PL011_REG_RESERVED1(BASE) HWREG32(BASE + 0x1C) argument
64 #define PL011_REG_ILPR(BASE) HWREG32(BASE + 0x20) argument
65 #define PL011_REG_IBRD(BASE) HWREG32(BASE + 0x24) argument
66 #define PL011_REG_FBRD(BASE) HWREG32(BASE + 0x28) argument
67 #define PL011_REG_LCRH(BASE) HWREG32(BASE + 0x2C) argument
68 #define PL011_REG_CR(BASE) HWREG32(BASE + 0x30) argument
[all …]
A Ddrv_gpio.h28 #define GPIO_REG_GPFSEL0(BASE) HWREG32(BASE + 0x00) argument
29 #define GPIO_REG_GPFSEL1(BASE) HWREG32(BASE + 0x04) argument
30 #define GPIO_REG_GPFSEL2(BASE) HWREG32(BASE + 0x08) argument
31 #define GPIO_REG_GPFSEL3(BASE) HWREG32(BASE + 0x0C) argument
32 #define GPIO_REG_GPFSEL4(BASE) HWREG32(BASE + 0x10) argument
33 #define GPIO_REG_GPFSEL5(BASE) HWREG32(BASE + 0x14) argument
34 #define GPIO_REG_REV0(BASE) HWREG32(BASE + 0x18) argument
35 #define GPIO_REG_GPSET0(BASE) HWREG32(BASE + 0x1C) argument
36 #define GPIO_REG_GPSET1(BASE) HWREG32(BASE + 0x20) argument
37 #define GPIO_REG_REV1(BASE) HWREG32(BASE + 0x24) argument
[all …]
A Ddrv_spi.h15 #define SPI_REG_CS(BASE) HWREG32(BASE + 0x00) argument
16 #define SPI_REG_FIFO(BASE) HWREG32(BASE + 0x04) argument
17 #define SPI_REG_CLK(BASE) HWREG32(BASE + 0x08) argument
18 #define SPI_REG_DLEN(BASE) HWREG32(BASE + 0x0C) argument
19 #define SPI_REG_LTOH(BASE) HWREG32(BASE + 0x10) argument
20 #define SPI_REG_DC(BASE) HWREG32(BASE + 0x14) argument
/bsp/raspberry-pi/raspi-dm2.0/drivers/
A Ddrv_uart.h59 #define PL011_REG_DR(BASE) HWREG32(BASE + 0x00) argument
60 #define PL011_REG_RSRECR(BASE) HWREG32(BASE + 0x04) argument
61 #define PL011_REG_RESERVED0(BASE) HWREG32(BASE + 0x08) argument
62 #define PL011_REG_FR(BASE) HWREG32(BASE + 0x18) argument
63 #define PL011_REG_RESERVED1(BASE) HWREG32(BASE + 0x1C) argument
64 #define PL011_REG_ILPR(BASE) HWREG32(BASE + 0x20) argument
65 #define PL011_REG_IBRD(BASE) HWREG32(BASE + 0x24) argument
66 #define PL011_REG_FBRD(BASE) HWREG32(BASE + 0x28) argument
67 #define PL011_REG_LCRH(BASE) HWREG32(BASE + 0x2C) argument
68 #define PL011_REG_CR(BASE) HWREG32(BASE + 0x30) argument
[all …]
/bsp/raspberry-pi/raspi4-32/driver/
A Ddrv_uart.h59 #define PL011_REG_DR(BASE) HWREG32(BASE + 0x00) argument
60 #define PL011_REG_RSRECR(BASE) HWREG32(BASE + 0x04) argument
61 #define PL011_REG_RESERVED0(BASE) HWREG32(BASE + 0x08) argument
62 #define PL011_REG_FR(BASE) HWREG32(BASE + 0x18) argument
63 #define PL011_REG_RESERVED1(BASE) HWREG32(BASE + 0x1C) argument
64 #define PL011_REG_ILPR(BASE) HWREG32(BASE + 0x20) argument
65 #define PL011_REG_IBRD(BASE) HWREG32(BASE + 0x24) argument
66 #define PL011_REG_FBRD(BASE) HWREG32(BASE + 0x28) argument
67 #define PL011_REG_LCRH(BASE) HWREG32(BASE + 0x2C) argument
68 #define PL011_REG_CR(BASE) HWREG32(BASE + 0x30) argument
[all …]
A Ddrv_gpio.h28 #define GPIO_REG_GPFSEL0(BASE) HWREG32(BASE + 0x00) argument
29 #define GPIO_REG_GPFSEL1(BASE) HWREG32(BASE + 0x04) argument
30 #define GPIO_REG_GPFSEL2(BASE) HWREG32(BASE + 0x08) argument
31 #define GPIO_REG_GPFSEL3(BASE) HWREG32(BASE + 0x0C) argument
32 #define GPIO_REG_GPFSEL4(BASE) HWREG32(BASE + 0x10) argument
33 #define GPIO_REG_GPFSEL5(BASE) HWREG32(BASE + 0x14) argument
34 #define GPIO_REG_REV0(BASE) HWREG32(BASE + 0x18) argument
35 #define GPIO_REG_GPSET0(BASE) HWREG32(BASE + 0x1C) argument
36 #define GPIO_REG_GPSET1(BASE) HWREG32(BASE + 0x20) argument
37 #define GPIO_REG_REV1(BASE) HWREG32(BASE + 0x24) argument
[all …]
A Ddrv_i2c.h16 #define BSC_C(BASE) __REG32(BASE + 0x0000) /* BSC Master Control */ argument
17 #define BSC_S(BASE) __REG32(BASE + 0x0004) /* BSC Master Status */ argument
18 #define BSC_DLEN(BASE) __REG32(BASE + 0x0008) /* BSC Master Data Length */ argument
19 #define BSC_A(BASE) __REG32(BASE + 0x000c) /* BSC Master Slave Address */ argument
20 #define BSC_FIFO(BASE) __REG32(BASE + 0x0010) /* BSC Master Data FIFO */ argument
21 #define BSC_DIV(BASE) __REG32(BASE + 0x0014) /* BSC Master Clock Divider */ argument
22 #define BSC_DEL(BASE) __REG32(BASE + 0x0018) /* BSC Master Data Delay */ argument
23 #define BSC_CLKT(BASE) __REG32(BASE + 0x001c) /* BSC Master Clock Stretch Timeout */ argument
A Ddrv_spi.h15 #define SPI_REG_CS(BASE) HWREG32(BASE + 0x00) argument
16 #define SPI_REG_FIFO(BASE) HWREG32(BASE + 0x04) argument
17 #define SPI_REG_CLK(BASE) HWREG32(BASE + 0x08) argument
18 #define SPI_REG_DLEN(BASE) HWREG32(BASE + 0x0C) argument
19 #define SPI_REG_LTOH(BASE) HWREG32(BASE + 0x10) argument
20 #define SPI_REG_DC(BASE) HWREG32(BASE + 0x14) argument
/bsp/raspberry-pi/raspi3-32/driver/
A Ddrv_uart.h17 #define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */ argument
18 #define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */ argument
19 #define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */ argument
22 #define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */ argument
23 #define AUX_MU_MCR_REG(BASE) HWREG32(BASE + 0x50) /* Mini Uart Modem Control 8bit */ argument
24 #define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */ argument
26 #define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */ argument
29 #define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */ argument
32 #define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */ argument
33 #define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */ argument
[all …]
A Draspi.h202 #define BCM283X_BSC_C(BASE) HWREG32(BASE + 0x0000) /* BSC Master Control */ argument
203 #define BCM283X_BSC_S(BASE) HWREG32(BASE + 0x0004) /* BSC Master Status */ argument
205 #define BCM283X_BSC_A(BASE) HWREG32(BASE + 0x000c) /* BSC Master Slave Address */ argument
206 #define BCM283X_BSC_FIFO(BASE) HWREG32(BASE + 0x0010) /* BSC Master Data FIFO */ argument
208 #define BCM283X_BSC_DEL(BASE) HWREG32(BASE + 0x0018) /* BSC Master Data Delay */ argument
240 #define BCM283X_SPI0_CS(BASE) HWREG32(BASE + 0x0000) /* SPI Master Control and Status */ argument
241 #define BCM283X_SPI0_FIFO(BASE) HWREG32(BASE + 0x0004) /* SPI Master TX and RX FIFOs */ argument
242 #define BCM283X_SPI0_CLK(BASE) HWREG32(BASE + 0x0008) /* SPI Master Clock Divider */ argument
243 #define BCM283X_SPI0_DLEN(BASE) HWREG32(BASE + 0x000c) /* SPI Master Data Length */ argument
244 #define BCM283X_SPI0_LTOH(BASE) HWREG32(BASE + 0x0010) /* SPI LOSSI mode TOH */ argument
[all …]
/bsp/raspberry-pi/raspi3-64/driver/
A Ddrv_uart.h18 #define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */ argument
19 #define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */ argument
20 #define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */ argument
23 #define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */ argument
24 #define AUX_MU_MCR_REG(BASE) HWREG32(BASE + 0x50) /* Mini Uart Modem Control 8bit */ argument
25 #define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */ argument
27 #define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */ argument
30 #define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */ argument
33 #define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */ argument
34 #define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */ argument
[all …]
A Draspi.h206 #define BCM283X_BSC_C(BASE) __REG32(BASE + 0x0000) /* BSC Master Control */ argument
207 #define BCM283X_BSC_S(BASE) __REG32(BASE + 0x0004) /* BSC Master Status */ argument
209 #define BCM283X_BSC_A(BASE) __REG32(BASE + 0x000c) /* BSC Master Slave Address */ argument
210 #define BCM283X_BSC_FIFO(BASE) __REG32(BASE + 0x0010) /* BSC Master Data FIFO */ argument
212 #define BCM283X_BSC_DEL(BASE) __REG32(BASE + 0x0018) /* BSC Master Data Delay */ argument
244 #define BCM283X_SPI0_CS(BASE) __REG32(BASE + 0x0000) /* SPI Master Control and Status */ argument
245 #define BCM283X_SPI0_FIFO(BASE) __REG32(BASE + 0x0004) /* SPI Master TX and RX FIFOs */ argument
246 #define BCM283X_SPI0_CLK(BASE) __REG32(BASE + 0x0008) /* SPI Master Clock Divider */ argument
247 #define BCM283X_SPI0_DLEN(BASE) __REG32(BASE + 0x000c) /* SPI Master Data Length */ argument
248 #define BCM283X_SPI0_LTOH(BASE) __REG32(BASE + 0x0010) /* SPI LOSSI mode TOH */ argument
[all …]
/bsp/raspberry-pi/raspi2/driver/
A Ddrv_uart.h18 #define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */ argument
19 #define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */ argument
20 #define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */ argument
23 #define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */ argument
24 #define AUX_MU_MCR_REG(BASE) HWREG32(BASE + 0x50) /* Mini Uart Modem Control 8bit */ argument
25 #define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */ argument
27 #define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */ argument
30 #define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */ argument
33 #define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */ argument
34 #define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */ argument
[all …]
/bsp/cvitek/drivers/
A Ddrv_sdhci.c48 uintptr_t BASE = (uintptr_t)base; in sdhci_set_card_clock() local
124 uintptr_t BASE = (uintptr_t)base; in SDIF_ChangeCardClock() local
172 …mmio_write_16(BASE + SDIF_CLK_CTRL, mmio_read_16(BASE + SDIF_CLK_CTRL) | 0xc); // enable PLL_ENAB… in SDIF_ChangeCardClock()
573 mmio_write_8(BASE + SDIF_PWR_CONTROL,mmio_read_8(BASE + SDIF_PWR_CONTROL) | 0x1); in sdhci_enable_card_power()
577 mmio_write_8(BASE + SDIF_PWR_CONTROL,mmio_read_8(BASE+ SDIF_PWR_CONTROL) & ~0x1); in sdhci_enable_card_power()
702 uintptr_t vendor_base = BASE + (mmio_read_16(BASE + P_VENDOR_SPECIFIC_AREA) & ((1<<12)-1)); in sdhci_phy_init()
738 mmio_write_16(BASE + SDIF_HOST_CONTROL2, mmio_read_16(BASE + SDIF_HOST_CONTROL2) | 1<<11); in sdhci_init()
739 mmio_write_16(BASE + SDIF_CLK_CTRL, mmio_read_16(BASE + SDIF_CLK_CTRL) & ~(0x1 << 5)); in sdhci_init()
742 mmio_write_16(BASE + SDIF_HOST_CONTROL2, mmio_read_16(BASE + SDIF_HOST_CONTROL2) | 0x1<<13); in sdhci_init()
761 mmio_write_16(BASE + SDIF_INT_STATUS, mmio_read_16(BASE + SDIF_INT_STATUS) | (0x1 << 6)); in sdhci_init()
[all …]
/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/
A Dft32f0xx_tim.h612 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ argument
613 ((BASE) == TIM_DMABase_CR2) || \
614 ((BASE) == TIM_DMABase_SMCR) || \
616 ((BASE) == TIM_DMABase_SR) || \
617 ((BASE) == TIM_DMABase_EGR) || \
621 ((BASE) == TIM_DMABase_CNT) || \
622 ((BASE) == TIM_DMABase_PSC) || \
623 ((BASE) == TIM_DMABase_ARR) || \
624 ((BASE) == TIM_DMABase_RCR) || \
630 ((BASE) == TIM_DMABase_DCR) || \
[all …]
/bsp/tkm32F499/Libraries/Hal_lib/inc/
A DHAL_tim.h548 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ argument
549 ((BASE) == TIM_DMABase_CR2) || \
550 ((BASE) == TIM_DMABase_SMCR) || \
551 ((BASE) == TIM_DMABase_DIER) || \
552 ((BASE) == TIM_DMABase_SR) || \
553 ((BASE) == TIM_DMABase_EGR) || \
554 ((BASE) == TIM_DMABase_CCMR1) || \
555 ((BASE) == TIM_DMABase_CCMR2) || \
556 ((BASE) == TIM_DMABase_CCER) || \
557 ((BASE) == TIM_DMABase_CNT) || \
[all …]
/bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/inc/
A DHAL_tim.h548 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ argument
549 ((BASE) == TIM_DMABase_CR2) || \
550 ((BASE) == TIM_DMABase_SMCR) || \
551 ((BASE) == TIM_DMABase_DIER) || \
552 ((BASE) == TIM_DMABase_SR) || \
553 ((BASE) == TIM_DMABase_EGR) || \
554 ((BASE) == TIM_DMABase_CCMR1) || \
555 ((BASE) == TIM_DMABase_CCMR2) || \
556 ((BASE) == TIM_DMABase_CCER) || \
557 ((BASE) == TIM_DMABase_CNT) || \
[all …]
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/inc/
A Dhk32f0xx_tim.h611 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ argument
612 ((BASE) == TIM_DMABase_CR2) || \
613 ((BASE) == TIM_DMABase_SMCR) || \
615 ((BASE) == TIM_DMABase_SR) || \
616 ((BASE) == TIM_DMABase_EGR) || \
620 ((BASE) == TIM_DMABase_CNT) || \
621 ((BASE) == TIM_DMABase_PSC) || \
622 ((BASE) == TIM_DMABase_ARR) || \
623 ((BASE) == TIM_DMABase_RCR) || \
629 ((BASE) == TIM_DMABase_DCR) || \
[all …]
/bsp/airm2m/air32f103/libraries/AIR32F10xLib/inc/
A Dair32f10x_tim.h606 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ argument
607 ((BASE) == TIM_DMABase_CR2) || \
608 ((BASE) == TIM_DMABase_SMCR) || \
609 ((BASE) == TIM_DMABase_DIER) || \
610 ((BASE) == TIM_DMABase_SR) || \
611 ((BASE) == TIM_DMABase_EGR) || \
615 ((BASE) == TIM_DMABase_CNT) || \
616 ((BASE) == TIM_DMABase_PSC) || \
617 ((BASE) == TIM_DMABase_ARR) || \
618 ((BASE) == TIM_DMABase_RCR) || \
[all …]
/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/
A Dn32g45x_tim.h575 #define IsTimDmaBase(BASE) … argument
576 …(((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) …
577 …|| ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGE…
578 …|| ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) || ((BASE) == TIM_DMAB…
579 …|| ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) …
580 …|| ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDA…
581 …|| ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMAB…
582 …|| ((BASE) == TIM_DMABASE_CAPCMPDAT5) || ((BASE) == TIM_DMABASE_CAPCMPDAT6) || ((BASE) == TIM_DMAB…
583 || ((BASE) == TIM_DMABASE_DMACTRL))
/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/
A Dn32g43x_tim.h573 #define IsTimDmaBase(BASE) … argument
574 …(((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) …
575 …|| ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGE…
576 …|| ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) || ((BASE) == TIM_DMAB…
577 …|| ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) …
578 …|| ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDA…
579 …|| ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMAB…
580 || ((BASE) == TIM_DMABASE_BKDT)|| ((BASE) == TIM_DMABASE_DMACTRL))
/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/
A Dn32l43x_tim.h573 #define IsTimDmaBase(BASE) … argument
574 …(((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) …
575 …|| ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGE…
576 …|| ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) …
577 …|| ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) …
578 …|| ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDA…
579 …|| ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMAB…
580 || ((BASE) == TIM_DMABASE_BKDT)|| ((BASE) == TIM_DMABASE_DMACTRL))
/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/
A Dn32wb452_tim.h573 #define IsTimDmaBase(BASE) … argument
574 …(((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) …
575 …|| ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGE…
576 …|| ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) …
577 …|| ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) …
578 …|| ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDA…
579 …|| ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMAB…
580 || ((BASE) == TIM_DMABASE_BKDT)|| ((BASE) == TIM_DMABASE_DMACTRL))
/bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/inc/
A DHAL_tim.h479 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ argument
480 ((BASE) == TIM_DMABase_CR2) || \
481 ((BASE) == TIM_DMABase_SMCR) || \
482 ((BASE) == TIM_DMABase_DIER) || \
483 ((BASE) == TIM_DMABase_SR) || \
484 ((BASE) == TIM_DMABase_EGR) || \
485 ((BASE) == TIM_DMABase_CCMR1) || \
486 ((BASE) == TIM_DMABase_CCMR2) || \
487 ((BASE) == TIM_DMABase_CCER) || \
488 ((BASE) == TIM_DMABase_CNT) || \
[all …]
/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/
A Dn32l40x_tim.h573 #define IsTimDmaBase(BASE) … argument
574 …(((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) …
575 …|| ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGE…
576 …|| ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) …
577 …|| ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) …
578 …|| ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDA…
579 …|| ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMAB…
580 || ((BASE) == TIM_DMABASE_BKDT)|| ((BASE) == TIM_DMABASE_DMACTRL))

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