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/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/
A Dgd32vf103_exti.h182 EXTI_0 = BIT(0), /*!< EXTI line 0 */
183 EXTI_1 = BIT(1), /*!< EXTI line 1 */
184 EXTI_2 = BIT(2), /*!< EXTI line 2 */
185 EXTI_3 = BIT(3), /*!< EXTI line 3 */
186 EXTI_4 = BIT(4), /*!< EXTI line 4 */
187 EXTI_5 = BIT(5), /*!< EXTI line 5 */
188 EXTI_6 = BIT(6), /*!< EXTI line 6 */
189 EXTI_7 = BIT(7), /*!< EXTI line 7 */
190 EXTI_8 = BIT(8), /*!< EXTI line 8 */
191 EXTI_9 = BIT(9), /*!< EXTI line 9 */
[all …]
A Dgd32vf103_gpio.h145 #define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
146 #define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */
147 #define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */
148 #define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */
149 #define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */
150 #define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */
151 #define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */
152 #define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */
153 #define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */
154 #define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */
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A Dgd32vf103_dbg.h56 #define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halt…
57 #define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halt…
62 #define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halte…
63 #define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halte…
64 #define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halte…
68 #define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halte…
74 …DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted …
80 …DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */
81 …DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */
82 …DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */
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A Dgd32vf103_rcu.h71 #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */
73 #define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */
75 #define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */
125 #define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */
126 #define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */
128 #define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */
140 #define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */
141 #define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */
146 #define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */
151 #define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */
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/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_usbfs_library/driver/Include/
A Ddrv_usb_regs.h203 #define GOTGINTF_HNPEND BIT(9) /*!< HNP end */
204 #define GOTGINTF_SRPEND BIT(8) /*!< SRP end */
227 #define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */
251 #define GINTF_RST BIT(12) /*!< USB reset */
322 #define GCCFG_PWRON BIT(16) /*!< power on */
401 #define HCHINTF_NYET BIT(6) /*!< NYET */
402 #define HCHINTF_ACK BIT(5) /*!< ACK */
403 #define HCHINTF_NAK BIT(4) /*!< NAK */
404 #define HCHINTF_STALL BIT(3) /*!< STALL */
513 #define DEP0CTL_SNAK BIT(27) /*!< set NAK */
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/bsp/allwinner/libraries/sunxi-hal/hal/source/uart/
A Duart.h75 #define UART_IIR_FEFLAG_MASK (BIT(6)|BIT(7))
76 #define UART_IIR_IID_MASK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
85 #define UART_FCR_RXTRG_MASK (BIT(6)|BIT(7))
90 #define UART_FCR_TXTRG_MASK (BIT(4)|BIT(5))
101 #define UART_LCR_PARITY_MASK (BIT(5)|BIT(4))
106 #define UART_LCR_DLEN_MASK (BIT(1)|BIT(0))
112 #define UART_MCR_MODE_MASK (BIT(7)|BIT(6))
124 #define UART_LSR_BI (BIT(4))
125 #define UART_LSR_FE (BIT(3))
126 #define UART_LSR_PE (BIT(2))
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/bsp/essemi/es32vf2264/libraries/RV_CORE/Device/EastSoft/ES32VF2264/Include/ES32VF2264/
A Dreg_uart.h56 #define UART_LCON_TXEN_MSK BIT(UART_LCON_TXEN_POS)
59 #define UART_LCON_RXEN_MSK BIT(UART_LCON_RXEN_POS)
62 #define UART_LCON_DBCEN_MSK BIT(UART_LCON_DBCEN_POS)
65 #define UART_LCON_BREAK_MSK BIT(UART_LCON_BREAK_POS)
68 #define UART_LCON_SWAP_MSK BIT(UART_LCON_SWAP_POS)
80 #define UART_LCON_MSB_MSK BIT(UART_LCON_MSB_POS)
83 #define UART_LCON_PS_MSK BIT(UART_LCON_PS_POS)
86 #define UART_LCON_PE_MSK BIT(UART_LCON_PE_POS)
89 #define UART_LCON_STOP_MSK BIT(UART_LCON_STOP_POS)
247 #define UART_IER_TBC_MSK BIT(UART_IER_TBC_POS)
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A Dreg_i2c.h60 # define I2C_CON1_SBC_MSK BIT(I2C_CON1_SBC_POS)
73 # define I2C_CON1_PE_MSK BIT(I2C_CON1_PE_POS)
200 # define I2C_STAT_TC_MSK BIT(I2C_STAT_TC_POS)
265 # define I2C_IER_TCR_MSK BIT(I2C_IER_TCR_POS)
268 # define I2C_IER_TC_MSK BIT(I2C_IER_TC_POS)
286 # define I2C_IER_TXE_MSK BIT(I2C_IER_TXE_POS)
318 # define I2C_IDR_TC_MSK BIT(I2C_IDR_TC_POS)
367 # define I2C_IVS_TC_MSK BIT(I2C_IVS_TC_POS)
417 # define I2C_RIF_TC_MSK BIT(I2C_RIF_TC_POS)
467 # define I2C_IFM_TC_MSK BIT(I2C_IFM_TC_POS)
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A Dreg_spi.h222 #define SPI_IER_FRE_MSK BIT(SPI_IER_FRE_POS)
240 #define SPI_IER_RXF_MSK BIT(SPI_IER_RXF_POS)
255 #define SPI_IER_TXE_MSK BIT(SPI_IER_TXE_POS)
260 #define SPI_IDR_FRE_MSK BIT(SPI_IDR_FRE_POS)
278 #define SPI_IDR_RXF_MSK BIT(SPI_IDR_RXF_POS)
293 #define SPI_IDR_TXE_MSK BIT(SPI_IDR_TXE_POS)
298 #define SPI_IVS_FRE_MSK BIT(SPI_IVS_FRE_POS)
316 #define SPI_IVS_RXF_MSK BIT(SPI_IVS_RXF_POS)
331 #define SPI_IVS_TXE_MSK BIT(SPI_IVS_TXE_POS)
336 #define SPI_RIF_FRE_MSK BIT(SPI_RIF_FRE_POS)
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A Dreg_usb.h35 #define USB_POWER_ISOUDT_MSK BIT(USB_POWER_ISOUDT_POS)
39 #define USB_POWER_RESET_MSK BIT(USB_POWER_RESET_POS)
42 #define USB_POWER_RESUME_MSK BIT(USB_POWER_RESUME_POS)
67 #define USB_SWCID_HOST_MSK BIT(USB_SWCID_HOST_POS)
233 #define USB_TXCSRH_ISO_MSK BIT(USB_TXCSRH_ISO_POS)
239 #define USB_TXCSRH_FDT_MSK BIT(USB_TXCSRH_FDT_POS)
712 #define USB_IER_CONIE_MSK BIT(USB_IER_CONIE_POS)
716 #define USB_IER_SOFIE_MSK BIT(USB_IER_SOFIE_POS)
724 #define USB_IER_BABIE_MSK BIT(USB_IER_BABIE_POS)
728 #define USB_IER_RESIE_MSK BIT(USB_IER_RESIE_POS)
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A Dreg_timer.h166 #define TIMER_IER_UIT_MSK BIT(TIMER_IER_UIT_POS)
171 #define TIMER_IDR_BRKI_MSK BIT(TIMER_IDR_BRKI_POS)
174 #define TIMER_IDR_TRGI_MSK BIT(TIMER_IDR_TRGI_POS)
177 #define TIMER_IDR_COMI_MSK BIT(TIMER_IDR_COMI_POS)
180 #define TIMER_IDR_CC4I_MSK BIT(TIMER_IDR_CC4I_POS)
183 #define TIMER_IDR_CC3I_MSK BIT(TIMER_IDR_CC3I_POS)
186 #define TIMER_IDR_CC2I_MSK BIT(TIMER_IDR_CC2I_POS)
192 #define TIMER_IDR_UI_MSK BIT(TIMER_IDR_UI_POS)
197 #define TIMER_IVS_BKI_MSK BIT(TIMER_IVS_BKI_POS)
218 #define TIMER_IVS_UEI_MSK BIT(TIMER_IVS_UEI_POS)
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A Dreg_rmu.h46 #define RMU_CR_BOREN_MSK BIT(RMU_CR_BOREN_POS)
54 #define RMU_RSTSR_CFG_MSK BIT(RMU_RSTSR_CFG_POS)
57 #define RMU_RSTSR_CPU_MSK BIT(RMU_RSTSR_CPU_POS)
60 #define RMU_RSTSR_MCU_MSK BIT(RMU_RSTSR_MCU_POS)
63 #define RMU_RSTSR_CHIP_MSK BIT(RMU_RSTSR_CHIP_POS)
69 #define RMU_RSTSR_WWDT_MSK BIT(RMU_RSTSR_WWDT_POS)
72 #define RMU_RSTSR_IWDT_MSK BIT(RMU_RSTSR_IWDT_POS)
78 #define RMU_RSTSR_BOR_MSK BIT(RMU_RSTSR_BOR_POS)
84 #define RMU_RSTSR_POR_MSK BIT(RMU_RSTSR_POR_POS)
89 #define RMU_CRSTSR_CFG_MSK BIT(RMU_CRSTSR_CFG_POS)
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A Dreg_cmu.h38 #define CMU_CSR_CFT_RDYN_MSK BIT(CMU_CSR_CFT_RDYN_POS)
41 #define CMU_CSR_CFT_STU_MSK BIT(CMU_CSR_CFT_STU_POS)
48 #define CMU_CSR_SYS_RDYN_MSK BIT(CMU_CSR_SYS_RDYN_POS)
69 #define CMU_CFGR_USBSW_MSK BIT(CMU_CFGR_USBSW_POS)
72 #define CMU_CFGR_I2SSW_MSK BIT(CMU_CFGR_I2SSW_POS)
154 #define CMU_HOSMCR_NMIE_MSK BIT(CMU_HOSMCR_NMIE_POS)
176 #define CMU_HOSMCR_EN_MSK BIT(CMU_HOSMCR_EN_POS)
181 #define CMU_PULMCR_NMIE_MSK BIT(CMU_PULMCR_NMIE_POS)
203 #define CMU_PULMCR_EN_MSK BIT(CMU_PULMCR_EN_POS)
236 #define CMU_BUZZCR_EN_MSK BIT(CMU_BUZZCR_EN_POS)
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A Dreg_csu.h42 #define CSU_CON_SYNCGEN_MSK BIT(CSU_CON_SYNCGEN_POS)
45 #define CSU_CON_AUTOEN_MSK BIT(CSU_CON_AUTOEN_POS)
48 #define CSU_CON_CNTEN_MSK BIT(CSU_CON_CNTEN_POS)
56 #define CSU_CFG_POLSEL_MSK BIT(CSU_CFG_POLSEL_POS)
90 #define CSU_IER_FHIT_MSK BIT(CSU_IER_FHIT_POS)
102 #define CSU_IER_FWARN_MSK BIT(CSU_IER_FWARN_POS)
110 #define CSU_IDR_FHIT_MSK BIT(CSU_IDR_FHIT_POS)
130 #define CSU_IVS_FHIT_MSK BIT(CSU_IVS_FHIT_POS)
150 #define CSU_RIF_FHIT_MSK BIT(CSU_RIF_FHIT_POS)
170 #define CSU_IFM_FHIT_MSK BIT(CSU_IFM_FHIT_POS)
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/bsp/nuvoton/libraries/nu_packages/DA9062/
A Dda9062_reg.h158 #define DA9062AA_WRITE_MODE_MASK BIT(6)
160 #define DA9062AA_REVERT_MASK BIT(7)
166 #define DA9062AA_DVC_BUSY_MASK BIT(2)
172 #define DA9062AA_GPI1_MASK BIT(1)
174 #define DA9062AA_GPI2_MASK BIT(2)
176 #define DA9062AA_GPI3_MASK BIT(3)
178 #define DA9062AA_GPI4_MASK BIT(4)
184 #define DA9062AA_LDO2_ILIM_MASK BIT(1)
186 #define DA9062AA_LDO3_ILIM_MASK BIT(2)
188 #define DA9062AA_LDO4_ILIM_MASK BIT(3)
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/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/
A Des32f065x.h320 #define PMU_CR_CWUF_MSK BIT(PMU_CR_CWUF_POS)
332 #define PMU_SR_WUF_MSK BIT(PMU_SR_WUF_POS)
1753 #define RTC_WPR_WP_MSK BIT(RTC_WPR_WP_POS)
1815 #define RTC_CON_GO_MSK BIT(RTC_CON_GO_POS)
2136 #define RTC_IER_WU_MSK BIT(RTC_IER_WU_POS)
2154 #define RTC_IER_TS_MSK BIT(RTC_IER_TS_POS)
2163 #define RTC_IER_YR_MSK BIT(RTC_IER_YR_POS)
2172 #define RTC_IER_HR_MSK BIT(RTC_IER_HR_POS)
3421 #define UART_SR_BF_MSK BIT(UART_SR_BF_POS)
3424 #define UART_SR_FE_MSK BIT(UART_SR_FE_POS)
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/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/
A Des32f36xx.h443 #define PMU_SR_WUF_MSK BIT(PMU_SR_WUF_POS)
1557 #define ECC_CON_IE_MSK BIT(ECC_CON_IE_POS)
2430 #define RTC_WPR_WP_MSK BIT(RTC_WPR_WP_POS)
2492 #define RTC_CON_GO_MSK BIT(RTC_CON_GO_POS)
2813 #define RTC_IER_WU_MSK BIT(RTC_IER_WU_POS)
2831 #define RTC_IER_TS_MSK BIT(RTC_IER_TS_POS)
2840 #define RTC_IER_YR_MSK BIT(RTC_IER_YR_POS)
2849 #define RTC_IER_HR_MSK BIT(RTC_IER_HR_POS)
6242 #define CRC_CR_RST_MSK BIT(CRC_CR_RST_POS)
6245 #define CRC_CR_EN_MSK BIT(CRC_CR_EN_POS)
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/bsp/allwinner/libraries/sunxi-hal/hal/source/sdmmc/
A D_sdhost.h275 #define SDC_WAIT_NONE BIT(0)
276 #define SDC_WAIT_CMD_DONE BIT(1)
277 #define SDC_WAIT_DATA_OVER BIT(2)
278 #define SDC_WAIT_AUTOCMD_DONE BIT(3)
279 #define SDC_WAIT_IDMA_DONE BIT(4)
280 #define SDC_WAIT_IDMA_ERR BIT(5)
281 #define SDC_WAIT_ERROR BIT(6)
284 #define SDC_WAIT_SWITCH1V8 BIT(7)
285 #define SDC_WAIT_FINALIZE BIT(8)
483 #define SDXC_RXWLFlag BIT(0)
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/bsp/allwinner_tina/drivers/
A Ddrv_sdio.h66 #define BIT(x) (1UL<<(x)) macro
109 #define SDXC_RESPONSE_CMD BIT(6)
110 #define SDXC_LONG_RESPONSE_CMD BIT(7)
137 #define SDXC_FIFO_RX_LEVEL BIT(0)
138 #define SDXC_FIFO_TX_LEVEL BIT(1)
139 #define SDXC_FIFO_EMPTY BIT(2)
140 #define SDXC_FIFO_FULL BIT(3)
141 #define SDXC_CARD_PRESENT BIT(8)
142 #define SDXC_CARD_BUSY BIT(9)
143 #define SDXC_FSM_BUSY BIT(10)
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/bsp/rx/drivers/
A Duart.c91 PORT2.ICR.BIT.B2 = 1; in rx_configure()
93 PORT2.DDR.BIT.B2 = 0; in rx_configure()
104 PORT2.DDR.BIT.B0 = 1; in rx_configure()
105 PORT2.DR.BIT.B0 = 1; in rx_configure()
106 PORT2.ICR.BIT.B0 = 1; in rx_configure()
107 PORT2.ICR.BIT.B1 = 1; in rx_configure()
126 PORTF.DR.BIT.B0 = 1; in rx_configure()
132 PORT2.DR.BIT.B6 = 1; in rx_configure()
151 PORT5.DR.BIT.B0 = 1; in rx_configure()
164 PORT1.DR.BIT.B3 = 1; in rx_configure()
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/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/
A Dccu-sun8iw20.c35 .enable = BIT(27),
36 .lock = BIT(28),
50 .enable = BIT(27),
51 .lock = BIT(28),
67 .enable = BIT(27),
68 .lock = BIT(28),
431 BIT(31) | BIT(30), 0);
566 BIT(31) | BIT(30), /* TODO:gate peri*/
744 BIT(31), 0);
1263 val &= ~BIT(1); in sunxi_ccu_init()
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/bsp/stm32/stm32mp157a-st-ev1/board/ports/
A Ddrv_pmic.h328 #define BIT(_x) (1UL << (_x)) macro
424 #define ICC_EVENT_ENABLED BIT(4)
425 #define PWRCTRL_POLARITY_HIGH BIT(3)
426 #define PWRCTRL_PIN_VALID BIT(2)
427 #define RESTART_REQUEST_ENABLED BIT(1)
428 #define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
434 #define WAKEUP_DETECTOR_DISABLED BIT(4)
435 #define PWRCTRL_PD_ACTIVE BIT(3)
436 #define PWRCTRL_PU_ACTIVE BIT(2)
437 #define WAKEUP_PD_ACTIVE BIT(1)
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/bsp/stm32/stm32mp157a-st-discovery/board/ports/
A Ddrv_pmic.h328 #define BIT(_x) (1UL << (_x)) macro
424 #define ICC_EVENT_ENABLED BIT(4)
425 #define PWRCTRL_POLARITY_HIGH BIT(3)
426 #define PWRCTRL_PIN_VALID BIT(2)
427 #define RESTART_REQUEST_ENABLED BIT(1)
428 #define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
434 #define WAKEUP_DETECTOR_DISABLED BIT(4)
435 #define PWRCTRL_PD_ACTIVE BIT(3)
436 #define PWRCTRL_PU_ACTIVE BIT(2)
437 #define WAKEUP_PD_ACTIVE BIT(1)
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/bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/
A Dhal_irq.h46 #define IRQ_FC_EVT_SW0 BIT(0)
47 #define IRQ_FC_EVT_SW1 BIT(1)
48 #define IRQ_FC_EVT_SW2 BIT(2)
49 #define IRQ_FC_EVT_SW3 BIT(3)
50 #define IRQ_FC_EVT_SW4 BIT(4)
51 #define IRQ_FC_EVT_SW5 BIT(5)
52 #define IRQ_FC_EVT_SW6 BIT(6)
53 #define IRQ_FC_EVT_SW7 BIT(7)
82 #define IRQ_FC_EVT_SOC_EVT BIT(26)
91 #define IRQ_FC_EVT_PERIPH0 BIT(30)
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/bsp/raspberry-pi/raspi3-32/driver/
A Ddrv_sdio.h24 #define SDXC_CmdDone BIT(0)
25 #define SDXC_DataDone BIT(1)
26 #define SDXC_BlockGap BIT(2)
27 #define SDXC_WriteRdy BIT(4)
28 #define SDXC_ReadRdy BIT(5)
29 #define SDXC_Card BIT(8)
30 #define SDXC_Retune BIT(12)
31 #define SDXC_BootAck BIT(13)
32 #define SDXC_EndBoot BIT(14)
50 #define SDXC_CMD_RSPNS_48busy BIT(16)|BIT(17)
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