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/bsp/acm32/acm32f4xx-nucleo/libraries/Device/
A DSystem_ACM32F4.h49 #define STOP_WAKEUP_GPIO_PIN2 BIT2
76 #define STANDBY_WAKEUP_SOURCE_IO3 BIT2
172 #define SCU_RCR_IWDTRST_EN BIT2
186 #define SCU_RSR_IWDTRST_F BIT2
215 #define SCU_IPRST_UART1RST BIT2
221 #define SCU_CCR1_SYS_PLL (BIT2)
249 #define SCU_CIR_RCHRDYIF BIT2
278 #define SCU_IPCKENR_UART1CLKEN BIT2
285 #define SCU_IPCKENR2_WDTCLKEN BIT2
304 #define SCU_XTHCR_READYTIME_4096 BIT2
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/bsp/acm32/acm32f0x0-nucleo/libraries/Device/
A DSystem_ACM32F0x0.h53 #define STOP_WAKEUP_GPIO_PIN2 BIT2
80 #define STANDBY_WAKEUP_SOURCE_IO3 BIT2
259 #define SCU_RCR_IWDTRST_EN BIT2
273 #define SCU_RSR_IWDTRST_F BIT2
302 #define SCU_IPRST_UART1RST BIT2
335 #define SCU_CIR_RCHRDYIF BIT2
364 #define SCU_IPCKENR_UART1CLKEN BIT2
371 #define SCU_IPCKENR2_WDTCLKEN BIT2
390 #define SCU_XTHCR_READYTIME_4096 BIT2
625 #define RPMU_CR_RTCSEL (BIT2|BIT3)
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/bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Src/
A DHAL_TIMER.c295 TIMx->CCMR1 |= (BIT2); in HAL_TIMER_Output_Config()
409 TIMx->CCMR2 |= (BIT2); in HAL_TIMER_Output_Config()
501 TIMx->CCMR1 &= (~BIT2|BIT3); in HAL_TIMER_Capture_Config()
520 TIMx->CCMR2 &= (~BIT2|BIT3); in HAL_TIMER_Capture_Config()
559 htim->Instance->SMCR &= (~(BIT0|BIT1|BIT2)); in HAL_TIMER_SelectClockSource()
667 htim->Instance->CR1 &= (~BIT2); //URS = 0 in HAL_TIMER_Base_Init()
779 TIMx->CCER |= BIT2; in HAL_TIM_PWM_Output_Start()
839 TIMx->CCER &= (~(BIT0 | BIT2)); in HAL_TIM_PWM_Output_Stop()
895 TIMx->CCER |= BIT2; in HAL_TIMER_OC_Start()
958 TIMx->CCER |= BIT2; in HAL_TIMER_OCxN_Start()
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/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/
A DHAL_TIMER.c312 TIMx->CCER &= (~BIT2); //disable OC1N in HAL_TIMER_Output_Config()
328 TIMx->CCMR1 |= (BIT2); in HAL_TIMER_Output_Config()
442 TIMx->CCMR2 |= (BIT2); in HAL_TIMER_Output_Config()
534 TIMx->CCMR1 &= (~BIT2|BIT3); in HAL_TIMER_Capture_Config()
553 TIMx->CCMR2 &= (~BIT2|BIT3); in HAL_TIMER_Capture_Config()
700 htim->Instance->CR1 &= (~BIT2); //URS = 0 in HAL_TIMER_Base_Init()
812 TIMx->CCER |= BIT2; in HAL_TIM_PWM_Output_Start()
872 TIMx->CCER &= (~(BIT0 | BIT2)); in HAL_TIM_PWM_Output_Stop()
928 TIMx->CCER |= BIT2; in HAL_TIMER_OC_Start()
991 TIMx->CCER |= BIT2; in HAL_TIMER_OCxN_Start()
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/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/
A DHAL_ADC.h15 #define ADC_CH_MASK (BIT4|BIT3|BIT2|BIT1|BIT0)
21 #define ADC_SR_JEOC (BIT2)
29 #define ADC_IE_JEOCIE (BIT2)
51 #define ADC_CR1_AWDCH_MASK (BIT4|BIT3|BIT2|BIT1|BIT0)
68 #define ADC_CR2_ADC_STP BIT2
73 #define ADC_SMPR_CH_MASK (BIT3|BIT2|BIT1|BIT0)
81 #define ADC_DIFF_DIFF2_A BIT2
94 #define ADC_SQR1_L (BIT3|BIT2|BIT1|BIT0)
111 #define ADC_SIGN_SIGN2_A BIT2
129 #define ADC_TSREF_ADJ_TD_GA_MASK (BIT4|BIT3|BIT2|BIT1)
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A DHAL_SPI.h23 #define SPI_CTL_CPHA BIT2
34 #define SPI_TX_CTL_MODE BIT2
62 #define SPI_IE_TX_FIFO_EMPTY_EN BIT2
79 #define SPI_STATUS_TX_FIFO_EMPTY BIT2
89 #define SPI_HOLD_WP_EN BIT2
98 #define SPI_PARA_ORD2 BIT2
A DHAL_CAN.h28 #define CAN_MOD_STM BIT2
34 #define CAN_CMR_RRB BIT2
40 #define CAN_SR_TBS BIT2
49 #define CAN_IR_EI BIT2
58 #define CAN_IER_EIE BIT2
A DHAL_TIMER.h207 #define TIM_IT_CC2 BIT2
227 #define TIM_EVENTSOURCE_CC2 BIT2 /*!< A capture/compare event is generated on c…
286 #define TIMER_SR_CC2IF BIT2
299 #define TIMER_INT_EN_CC2 BIT2
370 #define TIM_IC1_PRESCALER_2 (BIT2)
372 #define TIM_IC1_PRESCALER_8 (BIT2|BIT3)
380 #define TIM_IC3_PRESCALER_2 (BIT2)
382 #define TIM_IC3_PRESCALER_8 (BIT2|BIT3)
A DHAL_RTC.h34 #define RTC_IE_MIN (BIT2)
53 #define RTC_SR_MIN (BIT2)
75 #define RTC_CR_FSEL (BIT0|BIT1|BIT2|BIT3)
95 #define RPMU_CR_RTCSEL (BIT2|BIT3)
108 #define RPMU_SR_WUP2F BIT2
123 #define RPMU_ANACR_XTLBYO BIT2
/bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/
A DHAL_ADC.h15 #define ADC_CH_MASK (BIT4|BIT3|BIT2|BIT1|BIT0)
21 #define ADC_SR_JEOC (BIT2)
29 #define ADC_IE_JEOCIE (BIT2)
51 #define ADC_CR1_AWDCH_MASK (BIT4|BIT3|BIT2|BIT1|BIT0)
68 #define ADC_CR2_ADC_STP BIT2
73 #define ADC_SMPR_CH_MASK (BIT3|BIT2|BIT1|BIT0)
81 #define ADC_DIFF_DIFF2_A BIT2
94 #define ADC_SQR1_L (BIT3|BIT2|BIT1|BIT0)
111 #define ADC_SIGN_SIGN2_A BIT2
130 #define ADC_TSREF_ADJ_TD_GA_MASK (BIT4|BIT3|BIT2|BIT1)
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A DHAL_SPI.h23 #define SPI_CTL_CPHA BIT2
34 #define SPI_TX_CTL_MODE BIT2
62 #define SPI_IE_TX_FIFO_EMPTY_EN BIT2
79 #define SPI_STATUS_TX_FIFO_EMPTY BIT2
89 #define SPI_HOLD_WP_EN BIT2
98 #define SPI_PARA_ORD2 BIT2
A DHAL_TIMER.h191 #define TIM_IT_CC2 BIT2
211 #define TIM_EVENTSOURCE_CC2 BIT2 /*!< A capture/compare event is generated on c…
270 #define TIMER_SR_CC2IF BIT2
283 #define TIMER_INT_EN_CC2 BIT2
354 #define TIM_IC1_PRESCALER_2 (BIT2)
356 #define TIM_IC1_PRESCALER_8 (BIT2|BIT3)
364 #define TIM_IC3_PRESCALER_2 (BIT2)
366 #define TIM_IC3_PRESCALER_8 (BIT2|BIT3)
A DHAL_CAN.h28 #define CAN_MOD_STM BIT2
34 #define CAN_CMR_RRB BIT2
40 #define CAN_SR_TBS BIT2
49 #define CAN_IR_EI BIT2
58 #define CAN_IER_EIE BIT2
A DHAL_TKEY.h18 #define TKEY_ISR_TIMEOUT (BIT2)
23 #define TKEY_IER_TIMEOUTIE (BIT2)
42 #define TKEY_CR_CREN (BIT2)
48 #define TKEY_SR_VCOUT1_ORG (BIT2)
A DHAL_RTC.h34 #define RTC_IE_MIN (BIT2)
53 #define RTC_SR_MIN (BIT2)
75 #define RTC_CR_FSEL (BIT0|BIT1|BIT2|BIT3)
95 #define RPMU_CR_RTCSEL (BIT2|BIT3)
108 #define RPMU_SR_WUP2F BIT2
123 #define RPMU_ANACR_XTLBYO BIT2
/bsp/apm32/libraries/APM32E10x_Library/APM32E10x_StdPeriphDriver/inc/
A Dapm32e10x_rcm.h199 RCM_INT_HSIRDY = BIT2, /*!< HSI ready interrupt */
212 RCM_AHB_PERIPH_SRAM = BIT2,
227 RCM_APB2_PERIPH_GPIOA = BIT2,
250 RCM_APB1_PERIPH_TMR4 = BIT2,
A Dapm32e10x_sci2c.h146 SCI2C_INT_RFF = BIT2, /*!< Rx FIFO full interrupt */
168 SCI2C_FLAG_TFE = BIT2, /*!< Tx FIFO empty flag */
175 SCI2C_FLAG_SRDL = BIT8 | BIT2 /*!< Slave receive data lost flag */
185 SCI2C_TAS_AD10SBNA = BIT2, /*!< 10 bit address mode second byte NACK */
/bsp/apm32/libraries/APM32S10x_Library/APM32S10x_StdPeriphDriver/inc/
A Dapm32s10x_rcm.h198 RCM_INT_HSIRDY = BIT2, /*!< HSI ready interrupt */
210 RCM_AHB_PERIPH_SRAM = BIT2,
223 RCM_APB2_PERIPH_GPIOA = BIT2,
242 RCM_APB1_PERIPH_TMR4 = BIT2,
A Dapm32s10x_qspi.h165 QSPI_FLAG_TFE = BIT2, /*!< TX FIFO empty flag */
178 QSPI_INT_RFU = BIT2, /*!< RX FIFO underflow interrupt */
191 QSPI_INT_FLAG_RFU = BIT2, /*!< RX FIFO underflow interrupt flag */
/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/
A Dapm32f10x_qspi.h166 QSPI_FLAG_TFE = BIT2, /*!< TX FIFO empty flag */
179 QSPI_INT_RFU = BIT2, /*!< RX FIFO underflow interrupt */
192 QSPI_INT_FLAG_RFU = BIT2, /*!< RX FIFO underflow interrupt flag */
A Dapm32f10x_sci2c.h110 SCI2C_INT_RFF = BIT2, /*!< Rx FIFO full interrupt */
132 SCI2C_FLAG_TFE = BIT2, /*!< Tx FIFO empty flag */
139 SCI2C_FLAG_SRDL = BIT8 | BIT2 /*!< Slave receive data lost flag */
149 SCI2C_TAS_AD10SBNA = BIT2, /*!< 10 bit address mode second byte NACK */
/bsp/apm32/libraries/APM32E10x_Library/APM32E10x_StdPeriphDriver/src/
A Dapm32e10x_misc.c212 SysTick->CTRL |= (uint32_t)BIT2; in SysTick_ConfigCLKSource()
216 SysTick->CTRL &= (uint32_t)(~BIT2); in SysTick_ConfigCLKSource()
/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/
A Dapm32f10x_misc.c211 SysTick->CTRL |= (uint32_t)BIT2; in SysTick_ConfigCLKSource()
215 SysTick->CTRL &= (uint32_t)(~BIT2); in SysTick_ConfigCLKSource()
/bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/
A Dapm32f4xx_misc.c215 SysTick->CTRL |= (uint32_t)BIT2; in SysTick_ConfigCLKSource()
219 SysTick->CTRL &= (uint32_t)(~BIT2); in SysTick_ConfigCLKSource()
/bsp/apm32/libraries/APM32S10x_Library/APM32S10x_StdPeriphDriver/src/
A Dapm32s10x_misc.c210 SysTick->CTRL |= (uint32_t)BIT2; in SysTick_ConfigCLKSource()
214 SysTick->CTRL &= (uint32_t)(~BIT2); in SysTick_ConfigCLKSource()

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