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Searched refs:BIT3 (Results 1 – 25 of 81) sorted by relevance

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/bsp/acm32/acm32f4xx-nucleo/libraries/Device/
A DSystem_ACM32F4.h50 #define STOP_WAKEUP_GPIO_PIN3 BIT3
77 #define STANDBY_WAKEUP_SOURCE_IO4 BIT3
171 #define SCU_RCR_LOCKRST_EN BIT3
185 #define SCU_RSR_LOCKRST_F BIT3
214 #define SCU_IPRST_UART2RST BIT3
248 #define SCU_CIR_XTHRDYIF BIT3
277 #define SCU_IPCKENR_UART2CLKEN BIT3
284 #define SCU_IPCKENR2_IWDTCLKEN BIT3
305 #define SCU_XTHCR_READYTIME_16384 BIT3
339 #define SCU_WMR_BOOTPIN BIT3
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/bsp/acm32/acm32f0x0-nucleo/libraries/Device/
A DSystem_ACM32F0x0.h54 #define STOP_WAKEUP_GPIO_PIN3 BIT3
81 #define STANDBY_WAKEUP_SOURCE_IO4 BIT3
258 #define SCU_RCR_LOCKRST_EN BIT3
272 #define SCU_RSR_LOCKRST_F BIT3
301 #define SCU_IPRST_UART2RST BIT3
334 #define SCU_CIR_XTHRDYIF BIT3
363 #define SCU_IPCKENR_UART2CLKEN BIT3
370 #define SCU_IPCKENR2_IWDTCLKEN BIT3
391 #define SCU_XTHCR_READYTIME_16384 BIT3
425 #define SCU_WMR_BOOTPIN BIT3
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/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/
A DHAL_ADC.h15 #define ADC_CH_MASK (BIT4|BIT3|BIT2|BIT1|BIT0)
20 #define ADC_SR_EOG (BIT3)
28 #define ADC_IE_EOGIE (BIT3)
51 #define ADC_CR1_AWDCH_MASK (BIT4|BIT3|BIT2|BIT1|BIT0)
67 #define ADC_CR2_DIV_MASK (BIT6|BIT5|BIT4|BIT3)
73 #define ADC_SMPR_CH_MASK (BIT3|BIT2|BIT1|BIT0)
80 #define ADC_DIFF_DIFF3_B BIT3
94 #define ADC_SQR1_L (BIT3|BIT2|BIT1|BIT0)
110 #define ADC_SIGN_SIGN3_B BIT3
129 #define ADC_TSREF_ADJ_TD_GA_MASK (BIT4|BIT3|BIT2|BIT1)
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A DHAL_SPI.h22 #define SPI_CTL_CPOL BIT3
33 #define SPI_TX_CTL_DMA_REQ_EN BIT3
44 #define SPI_RX_CTL_DMA_REQ_EN BIT3
61 #define SPI_IE_TX_FIFO_FULL_EN BIT3
78 #define SPI_STATUS_TX_FIFO_FULL BIT3
88 #define SPI_HOLD_EN BIT3
97 #define SPI_CON_RD_EN BIT3
A DHAL_TIMER.h208 #define TIM_IT_CC3 BIT3
228 #define TIM_EVENTSOURCE_CC3 BIT3 /*!< A capture/compare event is generated on c…
287 #define TIMER_SR_CC3IF BIT3
300 #define TIMER_INT_EN_CC3 BIT3
371 #define TIM_IC1_PRESCALER_4 (BIT3)
372 #define TIM_IC1_PRESCALER_8 (BIT2|BIT3)
381 #define TIM_IC3_PRESCALER_4 (BIT3)
382 #define TIM_IC3_PRESCALER_8 (BIT2|BIT3)
418 #define TIM_CC1_SLAVE_CAPTURE_POL_BOTH (BIT1 | BIT3)
A DHAL_CAN.h29 #define CAN_MOD_AFM BIT3
35 #define CAN_CMR_CDO BIT3
41 #define CAN_SR_TCS BIT3
50 #define CAN_IR_DOI BIT3
59 #define CAN_IER_DOIE BIT3
A DHAL_RTC.h33 #define RTC_IE_SEC (BIT3)
52 #define RTC_SR_SEC (BIT3)
75 #define RTC_CR_FSEL (BIT0|BIT1|BIT2|BIT3)
95 #define RPMU_CR_RTCSEL (BIT2|BIT3)
107 #define RPMU_SR_WUP3F BIT3
121 #define RPMU_ANACR_XTLDRV_0 BIT3
122 #define RPMU_ANACR_XTLDRV (BIT3|BIT4|BIT5)
A DHAL_UART.h23 #define UART_FR_BUSY BIT3
29 #define UART_LCRH_STP2 BIT3
41 #define UART_IFLS_RXIFLSEL (BIT3|BIT4|BIT5)
/bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/
A DHAL_ADC.h15 #define ADC_CH_MASK (BIT4|BIT3|BIT2|BIT1|BIT0)
20 #define ADC_SR_EOG (BIT3)
28 #define ADC_IE_EOGIE (BIT3)
51 #define ADC_CR1_AWDCH_MASK (BIT4|BIT3|BIT2|BIT1|BIT0)
67 #define ADC_CR2_DIV_MASK (BIT6|BIT5|BIT4|BIT3)
73 #define ADC_SMPR_CH_MASK (BIT3|BIT2|BIT1|BIT0)
80 #define ADC_DIFF_DIFF3_B BIT3
94 #define ADC_SQR1_L (BIT3|BIT2|BIT1|BIT0)
110 #define ADC_SIGN_SIGN3_B BIT3
130 #define ADC_TSREF_ADJ_TD_GA_MASK (BIT4|BIT3|BIT2|BIT1)
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A DHAL_SPI.h22 #define SPI_CTL_CPOL BIT3
33 #define SPI_TX_CTL_DMA_REQ_EN BIT3
44 #define SPI_RX_CTL_DMA_REQ_EN BIT3
61 #define SPI_IE_TX_FIFO_FULL_EN BIT3
78 #define SPI_STATUS_TX_FIFO_FULL BIT3
88 #define SPI_HOLD_EN BIT3
97 #define SPI_CON_RD_EN BIT3
A DHAL_TIMER.h192 #define TIM_IT_CC3 BIT3
212 #define TIM_EVENTSOURCE_CC3 BIT3 /*!< A capture/compare event is generated on c…
271 #define TIMER_SR_CC3IF BIT3
284 #define TIMER_INT_EN_CC3 BIT3
355 #define TIM_IC1_PRESCALER_4 (BIT3)
356 #define TIM_IC1_PRESCALER_8 (BIT2|BIT3)
365 #define TIM_IC3_PRESCALER_4 (BIT3)
366 #define TIM_IC3_PRESCALER_8 (BIT2|BIT3)
402 #define TIM_CC1_SLAVE_CAPTURE_POL_BOTH (BIT1 | BIT3)
A DHAL_CAN.h29 #define CAN_MOD_AFM BIT3
35 #define CAN_CMR_CDO BIT3
41 #define CAN_SR_TCS BIT3
50 #define CAN_IR_DOI BIT3
59 #define CAN_IER_DOIE BIT3
A DHAL_RTC.h33 #define RTC_IE_SEC (BIT3)
52 #define RTC_SR_SEC (BIT3)
75 #define RTC_CR_FSEL (BIT0|BIT1|BIT2|BIT3)
95 #define RPMU_CR_RTCSEL (BIT2|BIT3)
107 #define RPMU_SR_WUP3F BIT3
121 #define RPMU_ANACR_XTLDRV_0 BIT3
122 #define RPMU_ANACR_XTLDRV (BIT3|BIT4|BIT5)
A DHAL_UART.h23 #define UART_FR_BUSY BIT3
29 #define UART_LCRH_STP2 BIT3
41 #define UART_IFLS_RXIFLSEL (BIT3|BIT4|BIT5)
A DHAL_TKEY.h17 #define TKEY_ISR_BUSY (BIT3)
41 #define TKEY_CR_SHIELDEN (BIT3)
47 #define TKEY_SR_VCOUT2_ORG (BIT3)
/bsp/apm32/libraries/APM32E10x_Library/APM32E10x_StdPeriphDriver/inc/
A Dapm32e10x_rcm.h200 RCM_INT_HSERDY = BIT3, /*!< HSE ready interrupt */
213 RCM_AHB_PERIPH_FPU = BIT3,
228 RCM_APB2_PERIPH_GPIOB = BIT3,
251 RCM_APB1_PERIPH_TMR5 = BIT3,
A Dapm32e10x_sci2c.h147 SCI2C_INT_TFO = BIT3, /*!< Tx FIFO onverflow interrupt */
169 SCI2C_FLAG_RFNE = BIT3, /*!< Rx FIFO not empty flag */
186 SCI2C_TAS_TDNA = BIT3, /*!< Tx data NACK */
/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/
A Dapm32f10x_qspi.h167 QSPI_FLAG_RFNE = BIT3, /*!< RX FIFO not empty flag */
180 QSPI_INT_RFO = BIT3, /*!< RX FIFO overflow interrupt */
193 QSPI_INT_FLAG_RFO = BIT3, /*!< RX FIFO overflow interrupt flag */
A Dapm32f10x_rcm.h337 RCM_INT_HSERDY = BIT3, /*!< HSE ready interrupt */
352 RCM_AHB_PERIPH_FPU = BIT3,
371 RCM_APB2_PERIPH_GPIOB = BIT3,
394 RCM_APB1_PERIPH_TMR5 = BIT3,
A Dapm32f10x_sci2c.h111 SCI2C_INT_TFO = BIT3, /*!< Tx FIFO onverflow interrupt */
133 SCI2C_FLAG_RFNE = BIT3, /*!< Rx FIFO not empty flag */
150 SCI2C_TAS_TDNA = BIT3, /*!< Tx data NACK */
/bsp/apm32/libraries/APM32S10x_Library/APM32S10x_StdPeriphDriver/inc/
A Dapm32s10x_qspi.h166 QSPI_FLAG_RFNE = BIT3, /*!< RX FIFO not empty flag */
179 QSPI_INT_RFO = BIT3, /*!< RX FIFO overflow interrupt */
192 QSPI_INT_FLAG_RFO = BIT3, /*!< RX FIFO overflow interrupt flag */
A Dapm32s10x_rcm.h199 RCM_INT_HSERDY = BIT3, /*!< HSE ready interrupt */
211 RCM_AHB_PERIPH_FPU = BIT3,
224 RCM_APB2_PERIPH_GPIOB = BIT3,
/bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/inc/
A Dapm32f4xx_rcm.h239 RCM_INT_HSERDY = BIT3, /*!< HSE ready interrupt */
253 RCM_AHB1_PERIPH_GPIOD = BIT3, /*!< Select GPIOD clock */
286 RCM_AHB2_PERIPH_SM = BIT3, /*!< Select SM clock */
301 RCM_APB1_PERIPH_TMR5 = BIT3, /*!< Select TMR5 clock */
/bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Src/
A DHAL_TIMER.c283 TIMx->CCER &= (~BIT3); in HAL_TIMER_Output_Config()
287 TIMx->CCER |= (BIT3); in HAL_TIMER_Output_Config()
297 TIMx->CCMR1 |= (BIT3); // preload enable in HAL_TIMER_Output_Config()
406 TIMx->CCMR2 |= (BIT3); // preload enable in HAL_TIMER_Output_Config()
501 TIMx->CCMR1 &= (~BIT2|BIT3); in HAL_TIMER_Capture_Config()
520 TIMx->CCMR2 &= (~BIT2|BIT3); in HAL_TIMER_Capture_Config()
747 htim->Instance->CR1 &= (~BIT3); in HAL_TIMER_OnePulse_Init()
751 htim->Instance->CR1 |= BIT3; in HAL_TIMER_OnePulse_Init()
1251 htim->Instance->SR &= (~(BIT3|BIT11)); in HAL_TIMER_Clear_Capture_Flag()
/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/
A DHAL_TIMER.c316 TIMx->CCER &= (~BIT3); in HAL_TIMER_Output_Config()
320 TIMx->CCER |= (BIT3); in HAL_TIMER_Output_Config()
330 TIMx->CCMR1 |= (BIT3); // preload enable in HAL_TIMER_Output_Config()
439 TIMx->CCMR2 |= (BIT3); // preload enable in HAL_TIMER_Output_Config()
534 TIMx->CCMR1 &= (~BIT2|BIT3); in HAL_TIMER_Capture_Config()
553 TIMx->CCMR2 &= (~BIT2|BIT3); in HAL_TIMER_Capture_Config()
780 htim->Instance->CR1 &= (~BIT3); in HAL_TIMER_OnePulse_Init()
784 htim->Instance->CR1 |= BIT3; in HAL_TIMER_OnePulse_Init()
1284 htim->Instance->SR &= (~(BIT3|BIT11)); in HAL_TIMER_Clear_Capture_Flag()

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