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Searched refs:BL_GET_REG_BITS_VAL (Results 1 – 25 of 36) sorted by relevance

12

/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/
A Dbl702_clock.c166 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); in Clock_Get_MCU_HClk_Div_Val()
175 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV); in Clock_Get_Peri_BClk_Div_Val()
184 div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV); in Clock_F32k_Mux_Output()
203 return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL); in Clock_Get_F32k_Sel_Val()
322 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV); in Clock_Get_SPI_Div_Val()
337 return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV); in Clock_Get_I2C_Div_Val()
394 return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_EN); in Clock_Get_GPADC_Clk_Sel_Val()
473 return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV); in Clock_Get_IR_Div_Val()
511 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2); in Clock_Get_SF_Clk_Sel2_Val()
551 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL); in Clock_Get_SF_Clk_Sel_Val()
[all …]
A Dbl702_pds.c130 tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) & ~(1 << pin); in PDS_Set_Pad_Config()
131 tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) & ~(1 << pin); in PDS_Set_Pad_Config()
135 tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) | (1 << pin); in PDS_Set_Pad_Config()
136 tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) & ~(1 << pin); in PDS_Set_Pad_Config()
140 tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) & ~(1 << pin); in PDS_Set_Pad_Config()
141 tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) | (1 << pin); in PDS_Set_Pad_Config()
145 tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) | (1 << pin); in PDS_Set_Pad_Config()
146 tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) | (1 << pin); in PDS_Set_Pad_Config()
539 return (PDS_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_STATE); in PDS_Get_PdsStstus()
582 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_RESET_EVENT); in PDS_Get_Reset_Event()
[all …]
A Dbl702_hbn.c562 return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH); in HBN_Get_PIR_Threshold()
600 return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL); in HBN_Get_PIR_Interval()
613 return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_MISC), HBN_R_BOR_OUT) ? SET : RESET; in HBN_Get_BOR_OUT_State()
816 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); in HBN_Set_XCLK_CLK_Sel()
856 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); in HBN_Set_ROOT_CLK_Sel()
1312 return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_PIN_WAKEUP_MODE); in HBN_Get_Pin_Wakeup_Mode()
1421 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); in HBN_Enable_AComp0_IRQ()
1445 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); in HBN_Disable_AComp0_IRQ()
1469 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); in HBN_Enable_AComp1_IRQ()
1493 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); in HBN_Disable_AComp1_IRQ()
[all …]
A Dbl702_glb.c130 switch (BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL)) { in GLB_Get_Root_CLK_Sel()
197 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV); in GLB_Get_BCLK_Div()
217 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); in GLB_Get_HCLK_Div()
562 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN); in GLB_Set_DMA_CLK()
1840 return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_TZ) ? SET : RESET; in GLB_BMX_Get_Status()
1842 return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_DEC) ? SET : RESET; in GLB_BMX_Get_Status()
2558 dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN); in GLB_Set_DIG_CLK_Sel()
2559 dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN); in GLB_Set_DIG_CLK_Sel()
3308 aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT); in GLB_GPIO_INPUT_Enable()
3565 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL); in GLB_GPIO_Get_Fun()
[all …]
A Dbl702_l1c.c111 finWayDisable = BL_GET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS); in L1C_Cache_Enable_Set()
536 return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_TZ) ? SET : RESET; in L1C_BMX_Get_Status()
538 return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_DEC) ? SET : RESET; in L1C_BMX_Get_Status()
A Dbl702_common.c104 if (BL_GET_REG_BITS_VAL(BL_RD_REG(L1C_BASE, L1C_CONFIG), L1C_IROM_2T_ACCESS)) { in ASM_Delay_Us()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/
A Dbl602_clock.c95 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN); in Clock_Xtal_Output()
197 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); in Clock_Get_MCU_HClk_Div_Val()
206 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV); in Clock_Get_Peri_BClk_Div_Val()
215 div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV); in Clock_F32k_Mux_Output()
234 return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL); in Clock_Get_F32k_Sel_Val()
325 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV); in Clock_Get_SPI_Div_Val()
340 return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV); in Clock_Get_I2C_Div_Val()
391 return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_EN); in Clock_Get_GPADC_Clk_Sel_Val()
467 return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV); in Clock_Get_IR_Div_Val()
516 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL); in Clock_Get_SF_Clk_Sel_Val()
[all …]
A Dbl602_hbn.c531 return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH); in HBN_Get_PIR_Threshold()
569 return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL); in HBN_Get_PIR_Interval()
582 return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_BOR_CFG), HBN_R_BOR_OUT) ? SET : RESET; in HBN_Get_BOR_OUT_State()
776 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); in HBN_Set_XCLK_CLK_Sel()
812 switch (BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL)) { in HBN_Get_Root_CLK_Sel()
844 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); in HBN_Set_ROOT_CLK_Sel()
1306 return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_PIN_WAKEUP_MODE); in HBN_Get_Pin_Wakeup_Mode()
1421 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); in HBN_Enable_AComp0_IRQ()
1445 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); in HBN_Disable_AComp0_IRQ()
1469 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); in HBN_Enable_AComp1_IRQ()
[all …]
A Dbl602_glb.c124 switch (BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL)) { in GLB_Get_Root_CLK_Sel()
199 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV); in GLB_Get_BCLK_Div()
219 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); in GLB_Get_HCLK_Div()
501 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN); in GLB_Set_DMA_CLK()
1112 return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_TZ) ? SET : RESET; in GLB_BMX_Get_Status()
1114 return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_DEC) ? SET : RESET; in GLB_BMX_Get_Status()
1668 dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN); in GLB_Set_DIG_CLK_Sel()
1669 dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN); in GLB_Set_DIG_CLK_Sel()
2286 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL); in GLB_GPIO_Get_Fun()
2288 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL); in GLB_GPIO_Get_Fun()
[all …]
A Dbl602_pds.c327 … return (PDS_PLL_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_PLL_STATE); in PDS_Get_PdsPllStstus()
340 return (PDS_RF_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_RF_STATE); in PDS_Get_PdsRfStstus()
353 return (PDS_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_STATE); in PDS_Get_PdsStstus()
665 if (0x49D39D == BL_GET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN)) { in PDS_Fix_Xtal_Settig()
A Dbl602_l1c.c317 return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_TZ) ? SET : RESET; in L1C_BMX_Get_Status()
319 return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_DEC) ? SET : RESET; in L1C_BMX_Get_Status()
A Dbl602_common.c69 if (BL_GET_REG_BITS_VAL(BL_RD_REG(L1C_BASE, L1C_CONFIG), L1C_IROM_2T_ACCESS)) { in ASM_Delay_Us()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/
A Dbl808_clock.c485 div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV); in Clock_F32k_Mux_Output()
504 return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL); in Clock_Get_F32k_Sel_Val()
1211 …return ((BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL2) << 1) | BL_GET_REG_BITS_VAL(tmpVal, GL… in Clock_Get_UART_Clk_Sel_Val()
1285 return BL_GET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL); in Clock_Get_PKA_Clk_Sel_Val()
1300 return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV); in Clock_Get_IR_Div_Val()
1309 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2); in Clock_Get_SF_Clk_Sel2_Val()
1352 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL); in Clock_Get_SF_Clk_Sel_Val()
1361 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV); in Clock_Get_SF_Div_Val()
1381 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL); in Clock_Get_SPI_Clk_Sel_Val()
1390 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV); in Clock_Get_SPI_Div_Val()
[all …]
A Dbl808_hbn.c446 return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH); in HBN_Get_PIR_Threshold()
484 return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL); in HBN_Get_PIR_Interval()
691 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); in HBN_Get_MCU_XCLK_Sel()
712 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); in HBN_Set_MCU_XCLK_Sel()
770 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); in HBN_Set_MCU_Root_CLK_Sel()
1044 return BL_GET_REG_BITS_VAL(tmpVal, HBN_CORE_UNHALT); in HBN_Get_Core_Unhalt_Config()
1066 unhalt = BL_GET_REG_BITS_VAL(tmpVal, HBN_CORE_UNHALT); in HBN_Set_Core_Reboot_Config()
1092 return BL_GET_REG_BITS_VAL(tmpVal, HBN_POWER_ON_MM); in HBN_Get_MM_Power_Config()
1136 return BL_GET_REG_BITS_VAL(tmpVal, HBN_HAND_OFF_SEL); in HBN_Get_Hand_Off_Config()
1739 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); in HBN_Enable_AComp0_IRQ()
[all …]
A Dbl808_pds.c127 tmpValPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PU_SET); in PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie()
134 tmpValPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PD_SET); in PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie()
141 tmpValIe = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_IE_SET); in PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie()
614 pwrOff = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_PWR_OFF); in PDS_Get_MM_System_Power_On_State()
615 isoEn = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_ISO_EN); in PDS_Get_MM_System_Power_On_State()
616 gateClk = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_GATE_CLK); in PDS_Get_MM_System_Power_On_State()
617 memStby = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_MEM_STBY); in PDS_Get_MM_System_Power_On_State()
618 pdsRst = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_PDS_RST); in PDS_Get_MM_System_Power_On_State()
A Dbl808_glb_gpio.c370 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL); in GLB_GPIO_Get_Fun()
389 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_I) ? SET : RESET; in GLB_GPIO_Read()
517 return BL_GET_REG_BITS_VAL(BL_RD_WORD(gpioCfgAddress), GLB_GPIO_0_INT_STAT) ? SET : RESET; in GLB_Get_GPIO_IntStatus()
750 return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143), GLB_GPIO_TX_FIFO_CNT); in GLB_GPIO_Fifo_GetCount()
A Dbl808_glb.c1705 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_STS_BCLK_PROT_DONE); in GLB_Set_MCU_System_CLK_Div()
1723 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_STS_PICO_CLK_PROT_DONE); in GLB_Set_MCU_System_CLK_Div()
1913 *dspBclkDiv = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV); in GLB_Get_DSP_System_CLK_Div()
1914 *dspClkDiv = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV); in GLB_Get_DSP_System_CLK_Div()
2161 rootclk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL); in GLB_Get_DSP_ROOT_CLK_Sel()
2249 pbrootclk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL); in GLB_Get_DSP_PBROOT_CLK_Sel()
2880 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA2_CLK_EN); in GLB_Set_DMA_CLK()
2891 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN); in GLB_Set_DMA_CLK()
3399 dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN); in GLB_Set_DIG_CLK_Sel()
3400 dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN); in GLB_Set_DIG_CLK_Sel()
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/
A Dbl616_clock.c233 div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV); in Clock_F32k_Mux_Output()
252 return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL); in Clock_Get_F32k_Sel_Val()
519 …return ((BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL2) << 1) | BL_GET_REG_BITS_VAL(tmpVal, GL… in Clock_Get_UART_Clk_Sel_Val()
550 return BL_GET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL); in Clock_Get_PKA_Clk_Sel_Val()
565 return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV); in Clock_Get_IR_Div_Val()
574 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2); in Clock_Get_SF_Clk_Sel2_Val()
617 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL); in Clock_Get_SF_Clk_Sel_Val()
626 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV); in Clock_Get_SF_Div_Val()
646 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL); in Clock_Get_SPI_Clk_Sel_Val()
655 return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV); in Clock_Get_SPI_Div_Val()
[all …]
A Dbl616_hbn.c472 return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH); in HBN_Get_PIR_Threshold()
511 return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL); in HBN_Get_PIR_Interval()
711 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); in HBN_Get_MCU_XCLK_Sel()
732 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); in HBN_Set_MCU_XCLK_Sel()
790 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); in HBN_Set_MCU_Root_CLK_Sel()
1061 return BL_GET_REG_BITS_VAL(tmpVal, HBN_CORE_UNHALT); in HBN_Get_Core_Unhalt_Config()
1083 unhalt = BL_GET_REG_BITS_VAL(tmpVal, HBN_CORE_UNHALT); in HBN_Set_Core_Reboot_Config()
1109 return BL_GET_REG_BITS_VAL(tmpVal, HBN_USER_BOOT_SEL); in HBN_Get_User_Boot_Config()
1222 *xtalType = BL_GET_REG_BITS_VAL(tmpVal, HBN_XTAL_TYPE); in HBN_Get_Xtal_Type()
1248 xtalType = BL_GET_REG_BITS_VAL(tmpVal, HBN_XTAL_TYPE); in HBN_Get_Xtal_Value()
[all …]
A Dbl616_glb_gpio.c377 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL); in GLB_GPIO_Get_Fun()
396 return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_I) ? SET : RESET; in GLB_GPIO_Read()
524 return BL_GET_REG_BITS_VAL(BL_RD_WORD(gpioCfgAddress), GLB_GPIO_0_INT_STAT) ? SET : RESET; in GLB_Get_GPIO_IntStatus()
757 return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143), GLB_GPIO_TX_FIFO_CNT); in GLB_GPIO_Fifo_GetCount()
A Dbl616_glb.c352 … return (GLB_MCU_MUXPLL_80M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL)); in GLB_Get_MCU_Muxpll_80M_Sel()
389 … return (GLB_ISP_MUXPLL_80M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_ISP_MUXPLL_80M_SEL)); in GLB_Get_ISP_Muxpll_80M_Sel()
970 tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_STS_BCLK_PROT_DONE); in GLB_Set_MCU_System_CLK_Div()
1000 *mcuClkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_HCLK_DIV); in GLB_Get_MCU_System_CLK_Div()
1001 *mcuPBclkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV); in GLB_Get_MCU_System_CLK_Div()
1244 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN); in GLB_Set_DMA_CLK()
1629 tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_SWAP_SET); in GLB_SPI_Sig_Swap_Set()
1740 dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN); in GLB_Set_DIG_CLK_Sel()
1741 dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN); in GLB_Set_DIG_CLK_Sel()
2013 return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_BMX_CFG0), GLB_STS_BMX_TIMEOUT_STS); in GLB_Get_BMX_TO_Status()
[all …]
A Dbl616_pds.c113 tmpValPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PU_SET); in PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie()
120 tmpValPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PD_SET); in PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie()
127 tmpValIe = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_IE_SET); in PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/
A Dbl616_common.h42 #define BL_GET_REG_BITS_VAL(val, bitname) (((val)&bitname##_MSK) >> bitname##_POS) macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/
A Dbl602_common.h34 #define BL_GET_REG_BITS_VAL(val, bitname) (((val)&bitname##_MSK) >> bitname##_POS) macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/
A Dbl808_common.h46 #define BL_GET_REG_BITS_VAL(val, bitname) (((val)&bitname##_MSK) >> bitname##_POS) macro

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