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Searched refs:BL_IS_REG_BIT_SET (Results 1 – 17 of 17) sorted by relevance

/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/
A Dbl808_glb_gpio.c555 …if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_… in GPIO_FIFO_IRQHandler()
561 …if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_… in GPIO_FIFO_IRQHandler()
567 …if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX… in GPIO_FIFO_IRQHandler()
907 if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT) || in GLB_GPIO_Fifo_GetIntStatus()
908 BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT) || in GLB_GPIO_Fifo_GetIntStatus()
909 BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT)) { in GLB_GPIO_Fifo_GetIntStatus()
917 return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT); in GLB_GPIO_Fifo_GetIntStatus()
920 return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT); in GLB_GPIO_Fifo_GetIntStatus()
923 return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT); in GLB_GPIO_Fifo_GetIntStatus()
A Dbl808_psram_uhs.c437 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT)); in PSram_UHS_Read_Reg()
457 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGR_DONE)); in PSram_UHS_Read_Reg()
537 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT)); in PSram_UHS_Write_Reg()
558 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE)); in PSram_UHS_Write_Reg()
637 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT)); in PSram_UHS_Construct_Cmd()
674 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE)); in PSram_UHS_Construct_Cmd()
697 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE)); in PSram_UHS_Construct_Cmd()
719 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE)); in PSram_UHS_Construct_Cmd()
739 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_SRFI_DONE)); in PSram_UHS_Construct_Cmd()
748 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_SRFO_DONE)); in PSram_UHS_Construct_Cmd()
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A Dbl808_sdh.c205 if (BL_IS_REG_BIT_SET(tmpVal, SDH_CMD_INHIBIT_DAT)) { in SDH_ConfigDataTranfer()
259 if (BL_IS_REG_BIT_SET(tmpVal, SDH_CMD_INHIBIT_CMD)) { in SDH_ConfigDataTranfer()
303 if (!BL_IS_REG_BIT_SET(tmpVal, SDH_DMA_EN)) { in SDH_ReadDataPort()
379 if (!BL_IS_REG_BIT_SET(tmpVal, SDH_DMA_EN)) { in SDH_WriteDataPort()
631 } while (!BL_IS_REG_BIT_SET(tmpVal, SDH_INT_CLK_STABLE)); in SDH_SetSdClock()
749 } while (BL_IS_REG_BIT_SET(tmpVal, SDH_SW_RST_ALL)); in SDH_Reset()
A Dbl808_aon.c163 } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120); in AON_Power_On_XTAL()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/
A Dbl616_glb_gpio.c562 …if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_… in GPIO_FIFO_IRQHandler()
568 …if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_… in GPIO_FIFO_IRQHandler()
574 …if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX… in GPIO_FIFO_IRQHandler()
914 if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT) || in GLB_GPIO_Fifo_GetIntStatus()
915 BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT) || in GLB_GPIO_Fifo_GetIntStatus()
916 BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT)) { in GLB_GPIO_Fifo_GetIntStatus()
924 return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT); in GLB_GPIO_Fifo_GetIntStatus()
927 return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT); in GLB_GPIO_Fifo_GetIntStatus()
930 return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT); in GLB_GPIO_Fifo_GetIntStatus()
A Dbl616_psram.c157 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_REG_CONFIG_GNT)); in PSram_Ctrl_Request()
217 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_R_DONE)); in PSram_Ctrl_Winbond_Read_Reg()
296 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_W_DONE)); in PSram_Ctrl_Winbond_Write_Reg()
341 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_R_DONE)); in PSram_Ctrl_ApMem_Read_Reg()
407 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_W_DONE)); in PSram_Ctrl_ApMem_Write_Reg()
498 return BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_TIMEOUT); in PSram_Ctrl_Get_Timeout_Flag()
A Dbl616_sdh.c205 if (BL_IS_REG_BIT_SET(tmpVal, SDH_CMD_INHIBIT_DAT)) { in SDH_ConfigDataTranfer()
259 if (BL_IS_REG_BIT_SET(tmpVal, SDH_CMD_INHIBIT_CMD)) { in SDH_ConfigDataTranfer()
303 if (!BL_IS_REG_BIT_SET(tmpVal, SDH_DMA_EN)) { in SDH_ReadDataPort()
379 if (!BL_IS_REG_BIT_SET(tmpVal, SDH_DMA_EN)) { in SDH_WriteDataPort()
631 } while (!BL_IS_REG_BIT_SET(tmpVal, SDH_INT_CLK_STABLE)); in SDH_SetSdClock()
750 } while (BL_IS_REG_BIT_SET(tmpVal, SDH_SW_RST_ALL)); in SDH_Reset()
A Dbl616_aon.c169 } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120); in AON_Power_On_XTAL()
A Dbl616_pm.c705 if (BL_IS_REG_BIT_SET(tmpVal, PDS_WAKEUP_BY_IRRX_EN)) { in pm_pds_mode_enter()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/
A Dbl602_l1c.c106 cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE); in L1C_Set_Wrap()
148 cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE); in L1C_Set_Way_Disable()
A Dbl602_aon.c171 } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120); in AON_Power_On_XTAL()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/
A Dbl702_l1c.c135 } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_INVALID_DONE) && cnt < 100); in L1C_Cache_Enable_Set()
158 } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_FLUSH_DONE) && cnt < 100); in L1C_Cache_Enable_Set()
327 cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE); in L1C_Set_Wrap()
A Dbl702_aon.c168 } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120); in AON_Power_On_XTAL()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/
A Dbl616_common.h44 #define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0) macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/
A Dbl602_common.h36 #define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0) macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/
A Dbl808_common.h48 #define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0) macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/
A Dbl702_common.h36 #define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0) macro

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