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Searched refs:BL_RD_REG (Results 1 – 25 of 47) sorted by relevance

12

/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/
A Dbl808_psram_uhs.c177 tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS); in power_up_ldo12uhs()
188 tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS); in power_up_ldo12uhs()
198 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50); in set_cen_ck_ckn()
203 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40); in set_cen_ck_ckn()
226 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_30); in set_or_uhs()
399 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); in Psram_UHS_Init()
408 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); in Psram_UHS_Init()
428 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC); in PSram_UHS_Read_Reg()
445 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); in PSram_UHS_Read_Reg()
460 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD); in PSram_UHS_Read_Reg()
[all …]
A Dbl808_tzc_sec.c112 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID); in Tzc_Sec_Set_Master_Group()
155 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S0); in Tzc_Sec_Set_Slave_Group()
164 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1); in Tzc_Sec_Set_Slave_Group()
177 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S2); in Tzc_Sec_Set_Slave_Group()
249 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_0); in Tzc_Sec_Set_Glb_Ctrl_Group()
255 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_2); in Tzc_Sec_Set_Glb_Ctrl_Group()
270 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_CTRL_0); in Tzc_Sec_Set_MM_Glb_Ctrl_Group()
276 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_CTRL_2); in Tzc_Sec_Set_MM_Glb_Ctrl_Group()
807 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2); in Tzc_Sec_Set_Se_Ctrl_Mode()
829 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2); in Tzc_Sec_Set_Sf_Ctrl_Mode()
[all …]
A Dbl808_pds.c206 tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT); in PDS_Set_GPIO_Pad_IntMode()
613 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); in PDS_Get_MM_System_Power_On_State()
642 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); in PDS_Power_On_MM_System()
650 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); in PDS_Power_On_MM_System()
655 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); in PDS_Power_On_MM_System()
660 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); in PDS_Power_On_MM_System()
665 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); in PDS_Power_On_MM_System()
797 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntMask()
833 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
837 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
[all …]
A Dbl808_hbn.c200 tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM); in HBN_Enable()
211 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Enable()
217 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Enable()
228 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in HBN_Enable()
239 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Enable()
258 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Enable()
279 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Reset()
544 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in HBN_Set_Ldo11_Aon_Vout()
565 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in HBN_Set_Ldo11_Rt_Vout()
984 return BL_RD_REG(HBN_BASE, HBN_RSV0); in HBN_Get_Status_Flag()
[all …]
A Dbl808_aon.c111 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_On_MBG()
133 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_Off_MBG()
153 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_On_XTAL()
162 tmpVal = BL_RD_REG(AON_BASE, AON_TSEN); in AON_Power_On_XTAL()
185 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); in AON_Set_Xtal_CapCode()
207 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); in AON_Get_Xtal_CapCode()
224 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_Off_XTAL()
245 tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP); in AON_Power_On_BG()
267 tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP); in AON_Power_Off_BG()
451 tmpVal = BL_RD_REG(AON_BASE, AON_MISC); in AON_LowPower_Enter_PDS0()
[all …]
A Dbl808_glb.c1057 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in GLB_Power_On_XTAL_And_PLL_CLK()
1689 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in GLB_Set_MCU_System_CLK_Div()
1694 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in GLB_Set_MCU_System_CLK_Div()
2953 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); in GLB_Set_IR_CLK()
2957 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); in GLB_Set_IR_CLK()
2961 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); in GLB_Set_IR_CLK()
3014 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1); in GLB_IR_LED_Driver_Enable()
3034 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1); in GLB_IR_LED_Driver_Disable()
3161 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in GLB_Set_SF_CLK()
3171 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in GLB_Set_SF_CLK()
[all …]
A Dbl808_clock.c502 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in Clock_Get_F32k_Sel_Val()
652 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in Clock_Get_MCU_XClk_Sel_Val()
662 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in Clock_Get_MCU_Root_Clk_Sel_Val()
689 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in Clock_Get_MCU_HClk_Div_Val()
698 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in Clock_Get_Peri_BClk_Div_Val()
935 tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0); in Clock_Get_EMI_Clk_Div_Val()
1298 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); in Clock_Get_IR_Div_Val()
1307 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in Clock_Get_SF_Clk_Sel2_Val()
1350 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in Clock_Get_SF_Clk_Sel_Val()
1359 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in Clock_Get_SF_Div_Val()
[all …]
A Dbl808_uhs_phy.c341 tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); in power_up_mm()
345 tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); in power_up_mm()
349 tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); in power_up_mm()
353 tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); in power_up_mm()
357 tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); in power_up_mm()
365 tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); in power_up_mm()
369 tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); in power_up_mm()
373 tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); in power_up_mm()
377 tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); in power_up_mm()
381 tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); in power_up_mm()
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/
A Dbl616_tzc_sec.c130 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID); in Tzc_Sec_Set_Master_Group()
155 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S0); in Tzc_Sec_Set_Slave_Group()
164 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1); in Tzc_Sec_Set_Slave_Group()
177 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S2); in Tzc_Sec_Set_Slave_Group()
190 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1A); in Tzc_Sec_Set_Slave_Group()
232 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_0); in Tzc_Sec_Set_Glb_Ctrl_Group()
238 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_2); in Tzc_Sec_Set_Glb_Ctrl_Group()
491 tmpVal = BL_RD_REG(AON_BASE, AON_TZC_HBNRAM_R0); in Tzc_Sec_HBNRAM_Access_Set()
497 tmpVal = BL_RD_REG(AON_BASE, AON_TZC_HBNRAM_CTRL); in Tzc_Sec_HBNRAM_Access_Set()
735 tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2); in Tzc_Sec_Set_Se_Ctrl_Mode()
[all …]
A Dbl616_aon.c113 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_On_MBG()
137 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_Off_MBG()
159 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_On_XTAL()
168 tmpVal = BL_RD_REG(AON_BASE, AON_TSEN); in AON_Power_On_XTAL()
193 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); in AON_Set_Xtal_CapCode()
217 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); in AON_Get_Xtal_CapCode()
236 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_Off_XTAL()
259 tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP); in AON_Power_On_BG()
283 tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP); in AON_Power_Off_BG()
511 tmpVal = BL_RD_REG(AON_BASE, AON_MISC); in AON_LowPower_Enter_PDS0()
[all …]
A Dbl616_hbn.c200 tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM); in HBN_Enable()
211 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Enable()
217 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Enable()
226 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in HBN_Enable()
237 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Enable()
256 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Enable()
278 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Reset()
572 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in HBN_Set_Ldo11_Aon_Vout()
594 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in HBN_Set_Ldo11_Rt_Vout()
1001 return BL_RD_REG(HBN_BASE, HBN_RSV0); in HBN_Get_Status_Flag()
[all …]
A Dbl616_psram.c113 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE); in PSram_Ctrl_Init()
147 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE); in PSram_Ctrl_Request()
174 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE); in PSram_Ctrl_Release()
202 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE); in PSram_Ctrl_Winbond_Read_Reg()
207 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE); in PSram_Ctrl_Winbond_Read_Reg()
281 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE); in PSram_Ctrl_Winbond_Write_Reg()
286 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE); in PSram_Ctrl_Winbond_Write_Reg()
326 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE); in PSram_Ctrl_ApMem_Read_Reg()
331 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE); in PSram_Ctrl_ApMem_Read_Reg()
392 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE); in PSram_Ctrl_ApMem_Write_Reg()
[all …]
A Dbl616_glb.c474 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in GLB_Power_On_XTAL_And_PLL_CLK()
954 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in GLB_Set_MCU_System_CLK_Div()
959 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in GLB_Set_MCU_System_CLK_Div()
963 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1); in GLB_Set_MCU_System_CLK_Div()
1205 tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0); in GLB_Set_ADC_CLK()
1305 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); in GLB_Set_IR_CLK()
1309 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); in GLB_Set_IR_CLK()
1313 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); in GLB_Set_IR_CLK()
1453 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in GLB_Set_SF_CLK()
1463 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in GLB_Set_SF_CLK()
[all …]
A Dbl616_pds.c192 tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT); in PDS_Set_GPIO_Pad_IntMode()
229 tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT); in PDS_Set_GPIO_Pad_IntClr()
249 tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT); in PDS_Set_GPIO_Pad_IntClr()
269 tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT); in PDS_Set_GPIO_Pad_IntClr()
370 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL); in PDS_Disable_GPIO_Keep()
376 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL5); in PDS_Disable_GPIO_Keep()
500 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_Enable()
595 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntMask()
631 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
635 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
[all …]
A Dbl616_clock.c250 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in Clock_Get_F32k_Sel_Val()
331 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in Clock_Get_MCU_XClk_Sel_Val()
341 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in Clock_Get_MCU_Root_Clk_Sel_Val()
368 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in Clock_Get_MCU_HClk_Div_Val()
377 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in Clock_Get_Peri_BClk_Div_Val()
563 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); in Clock_Get_IR_Div_Val()
572 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in Clock_Get_SF_Clk_Sel2_Val()
615 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in Clock_Get_SF_Clk_Sel_Val()
624 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in Clock_Get_SF_Div_Val()
644 tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0); in Clock_Get_SPI_Clk_Sel_Val()
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/
A Dbl702_glb.c972 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in GLB_SW_System_Reset()
1028 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in GLB_SW_CPU_Reset()
1084 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in GLB_SW_POR_Reset()
2726 tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); in GLB_Power_Off_DLL()
2753 tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); in GLB_Power_On_DLL()
2769 tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); in GLB_Power_On_DLL()
2774 tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); in GLB_Power_On_DLL()
2781 tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); in GLB_Power_On_DLL()
2788 tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); in GLB_Power_On_DLL()
2814 tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); in GLB_Enable_DLL_All_Clks()
[all …]
A Dbl702_clock.c108 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_MCU_XClk_Sel_Val()
118 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_MCU_Root_Clk_Sel_Val()
164 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_MCU_HClk_Div_Val()
173 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_Peri_BClk_Div_Val()
201 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in Clock_Get_F32k_Sel_Val()
296 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in Clock_Get_UART_Clk_Sel_Val()
305 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); in Clock_Get_UART_Div_Val()
320 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); in Clock_Get_SPI_Div_Val()
335 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); in Clock_Get_I2C_Div_Val()
392 tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); in Clock_Get_GPADC_Clk_Sel_Val()
[all …]
A Dbl702_hbn.c252 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Enable_Ext()
258 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in HBN_Enable_Ext()
269 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Enable_Ext()
302 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Enable_Ext()
325 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Reset()
355 tmp[0] = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_App_Reset()
401 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Disable()
662 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in HBN_Set_Ldo11_Aon_Vout()
683 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in HBN_Set_Ldo11_Rt_Vout()
1049 return BL_RD_REG(HBN_BASE, HBN_RSV0); in HBN_Get_Status_Flag()
[all …]
A Dbl702_pds.c339 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntEn()
396 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntMask()
488 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
492 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
496 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
554 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_Clear_Reset_Event()
558 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_Clear_Reset_Event()
562 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_Clear_Reset_Event()
581 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_Get_Reset_Event()
1213 pdsCtl = BL_RD_REG(PDS_BASE, PDS_CTL); in PDS_Auto_Enable()
[all …]
A Dbl702_aon.c112 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_On_MBG()
136 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_Off_MBG()
158 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_On_XTAL()
167 tmpVal = BL_RD_REG(AON_BASE, AON_TSEN); in AON_Power_On_XTAL()
192 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); in AON_Set_Xtal_CapCode()
215 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); in AON_Get_Xtal_CapCode()
232 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); in AON_Set_Xtal_CapCode_Extra()
256 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_Off_XTAL()
448 tmpVal = BL_RD_REG(AON_BASE, AON_MISC); in AON_LowPower_Enter_PDS0()
497 tmpVal = BL_RD_REG(AON_BASE, AON_MISC); in AON_LowPower_Exit_PDS0()
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/
A Dbl602_hbn.c215 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Enable_Ext()
221 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in HBN_Enable_Ext()
232 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Enable_Ext()
271 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Enable_Ext()
294 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Reset()
324 tmp[0] = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_App_Reset()
332 tmp[8] = BL_RD_REG(HBN_BASE, HBN_SRAM); in HBN_App_Reset()
370 tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); in HBN_Disable()
633 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in HBN_Set_Ldo11_Aon_Vout()
1043 return BL_RD_REG(HBN_BASE, HBN_RSV0); in HBN_Get_Status_Flag()
[all …]
A Dbl602_clock.c94 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM); in Clock_Xtal_Output()
139 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_MCU_XClk_Sel_Val()
149 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_MCU_Root_Clk_Sel_Val()
195 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_MCU_HClk_Div_Val()
204 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_Peri_BClk_Div_Val()
232 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in Clock_Get_F32k_Sel_Val()
299 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in Clock_Get_UART_Clk_Sel_Val()
308 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); in Clock_Get_UART_Div_Val()
323 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); in Clock_Get_SPI_Div_Val()
338 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); in Clock_Get_I2C_Div_Val()
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A Dbl602_aon.c113 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_On_MBG()
138 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_Off_MBG()
161 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_On_XTAL()
170 tmpVal = BL_RD_REG(AON_BASE, AON_TSEN); in AON_Power_On_XTAL()
196 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); in AON_Set_Xtal_CapCode()
221 tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); in AON_Get_Xtal_CapCode()
241 tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); in AON_Power_Off_XTAL()
265 tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP); in AON_Power_On_BG()
459 tmpVal = BL_RD_REG(AON_BASE, AON_MISC); in AON_LowPower_Enter_PDS0()
470 tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); in AON_LowPower_Enter_PDS0()
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A Dbl602_glb.c122 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in GLB_Get_Root_CLK_Sel()
781 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in GLB_SW_System_Reset()
837 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in GLB_SW_CPU_Reset()
893 tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); in GLB_SW_POR_Reset()
1338 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); in GLB_UART_Sig_Swap_Set()
1359 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); in GLB_JTAG_Sig_Swap_Set()
1378 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); in GLB_Swap_SPI_0_MOSI_With_MISO()
1399 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); in GLB_Set_SPI_0_ACT_MOD_Sel()
1420 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); in GLB_Select_Internal_Flash()
1442 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); in GLB_Select_External_Flash()
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A Dbl602_pds.c147 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_Enable()
151 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_Enable()
206 tmpVal = BL_RD_REG(GLB_BASE, GLB_MBIST_CTL); in PDS_RAM_Config()
217 tmpVal = BL_RD_REG(GLB_BASE, GLB_MBIST_CTL); in PDS_RAM_Config()
264 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntMask()
302 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
306 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
310 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
508 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_CP); in PDS_Power_On_PLL()
527 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_RZ); in PDS_Power_On_PLL()
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