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Searched refs:BSP_CFG_CPUCLK_DIV (Results 1 – 19 of 19) sorted by relevance

/bsp/renesas/ra8m1-ek/ra_gen/
A Dbsp_clock_cfg.h37 #define BSP_CFG_CPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CPUCLK Div /1 */ macro
/bsp/renesas/ra8d1-ek/ra_gen/
A Dbsp_clock_cfg.h38 #define BSP_CFG_CPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CPUCLK Div /1 */ macro
/bsp/renesas/ra8d1-vision-board/ra_gen/
A Dbsp_clock_cfg.h38 #define BSP_CFG_CPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CPUCLK Div /1 */ macro
/bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c196 #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU)
969 if (BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1) in bsp_prv_clock_set()
981 if (BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1) in bsp_prv_clock_set()
1191 #if BSP_CFG_ICLK_DIV == BSP_CFG_CPUCLK_DIV in bsp_prv_clock_set_hard_reset()
1195 #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 in bsp_prv_clock_set_hard_reset()
1206 #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 in bsp_prv_clock_set_hard_reset()
A Dbsp_clocks.h131 #define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV)
/bsp/renesas/ra8m1-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c196 #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU)
967 if (BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1) in bsp_prv_clock_set()
979 if (BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1) in bsp_prv_clock_set()
1173 #if BSP_CFG_ICLK_DIV == BSP_CFG_CPUCLK_DIV in bsp_prv_clock_set_hard_reset()
1177 #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 in bsp_prv_clock_set_hard_reset()
1188 #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 in bsp_prv_clock_set_hard_reset()
A Dbsp_clocks.h131 #define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV)
/bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c196 #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU)
969 if (BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1) in bsp_prv_clock_set()
981 if (BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1) in bsp_prv_clock_set()
1191 #if BSP_CFG_ICLK_DIV == BSP_CFG_CPUCLK_DIV in bsp_prv_clock_set_hard_reset()
1195 #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 in bsp_prv_clock_set_hard_reset()
1206 #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 in bsp_prv_clock_set_hard_reset()
A Dbsp_clocks.h131 #define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV)
/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c196 #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU)
969 if (BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1) in bsp_prv_clock_set()
981 if (BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1) in bsp_prv_clock_set()
1191 #if BSP_CFG_ICLK_DIV == BSP_CFG_CPUCLK_DIV in bsp_prv_clock_set_hard_reset()
1195 #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 in bsp_prv_clock_set_hard_reset()
1206 #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 in bsp_prv_clock_set_hard_reset()
A Dbsp_clocks.h131 #define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV)
/bsp/renesas/ra6e2-fpb/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c221 #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU)
1664 #if BSP_CFG_ICLK_DIV == BSP_CFG_CPUCLK_DIV in bsp_prv_clock_set_hard_reset()
1668 #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 in bsp_prv_clock_set_hard_reset()
1718 #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 in bsp_prv_clock_set_hard_reset()
A Dbsp_clocks.h143 #define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV)
/bsp/renesas/ra4e2-eco/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c232 #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU)
1788 #if BSP_CFG_ICLK_DIV == BSP_CFG_CPUCLK_DIV in bsp_prv_clock_set_hard_reset()
1792 #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 in bsp_prv_clock_set_hard_reset()
1842 #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 in bsp_prv_clock_set_hard_reset()
A Dbsp_clocks.h142 #define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV)
/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.h131 #define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV)
A Dbsp_clocks.c193 #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU)
/bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.h131 #define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV)
A Dbsp_clocks.c193 #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU)

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