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Searched refs:BSP_CFG_FSELCANFD (Results 1 – 6 of 6) sorted by relevance

/bsp/renesas/rzn2l_etherkit/rzn_gen/
A Dbsp_clock_cfg.h39 #define BSP_CFG_FSELCANFD (BSP_CLOCKS_CANFD_CLOCK_40_MHZ) /* PCLKCAN 40MHz */ macro
/bsp/renesas/rzn2l_rsk/rzn_gen/
A Dbsp_clock_cfg.h39 #define BSP_CFG_FSELCANFD (BSP_CLOCKS_CANFD_CLOCK_40_MHZ) /* PCLKCAN 40MHz */ macro
/bsp/renesas/rzt2m_rsk/rzt_gen/
A Dbsp_clock_cfg.h40 #define BSP_CFG_FSELCANFD (BSP_CLOCKS_CANFD_CLOCK_40_MHZ) /* PCLKCAN 40MHz */ macro
/bsp/renesas/rzn2l_etherkit/rzn/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c42 #define BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS ((BSP_CFG_FSELCANFD & 1U) << 20U)
/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c42 #define BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS ((BSP_CFG_FSELCANFD & 1U) << 20U)
/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c42 #define BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS ((BSP_CFG_FSELCANFD & 1U) << 20U)

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