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Searched refs:BSP_CFG_FSELCPU0 (Results 1 – 6 of 6) sorted by relevance

/bsp/renesas/rzn2l_etherkit/rzn_gen/
A Dbsp_clock_cfg.h27 #define BSP_CFG_FSELCPU0 (BSP_CLOCKS_FSELCPU0_ICLK_MUL2) /* CPU0CLK Mulx2 */ macro
/bsp/renesas/rzn2l_rsk/rzn_gen/
A Dbsp_clock_cfg.h27 #define BSP_CFG_FSELCPU0 (BSP_CLOCKS_FSELCPU0_ICLK_MUL2) /* CPU0CLK Mulx2 */ macro
/bsp/renesas/rzt2m_rsk/rzt_gen/
A Dbsp_clock_cfg.h37 #define BSP_CFG_FSELCPU0 (BSP_CLOCKS_FSELCPU0_ICLK_MUL1) /* CPU0CLK Mul x1 */ macro
/bsp/renesas/rzn2l_etherkit/rzn/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c55 #define BSP_PRV_STARTUP_SCKCR2_FSELCPU0_BITS (BSP_CFG_FSELCPU0 & 3U)
/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c55 #define BSP_PRV_STARTUP_SCKCR2_FSELCPU0_BITS (BSP_CFG_FSELCPU0 & 3U)
/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c55 #define BSP_PRV_STARTUP_SCKCR2_FSELCPU0_BITS (BSP_CFG_FSELCPU0 & 3U)

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