| /bsp/renesas/ra6m3-ek/ra_gen/ |
| A D | bsp_clock_cfg.h | 13 #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ macro
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| /bsp/renesas/ra6m3-hmi-board/ra_gen/ |
| A D | bsp_clock_cfg.h | 13 #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ macro
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| /bsp/renesas/ra4m2-eco/ra_gen/ |
| A D | bsp_clock_cfg.h | 18 #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ macro
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| /bsp/renesas/ra6m4-cpk/ra_gen/ |
| A D | bsp_clock_cfg.h | 19 #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ macro
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| /bsp/renesas/ra6m4-iot/ra_gen/ |
| A D | bsp_clock_cfg.h | 19 #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ macro
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| /bsp/renesas/ra4e2-eco/ra_gen/ |
| A D | bsp_clock_cfg.h | 18 #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ macro
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| /bsp/renesas/ra6e2-fpb/ra_gen/ |
| A D | bsp_clock_cfg.h | 18 #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ macro
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| /bsp/renesas/ebf_qi_min_6m5/ra_gen/ |
| A D | bsp_clock_cfg.h | 22 #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ macro
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| /bsp/renesas/ra8m1-ek/ra_gen/ |
| A D | bsp_clock_cfg.h | 39 #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKA Div /4 */ macro
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| /bsp/renesas/ra8d1-ek/ra_gen/ |
| A D | bsp_clock_cfg.h | 40 #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKA Div /4 */ macro
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| /bsp/renesas/ra8d1-vision-board/ra_gen/ |
| A D | bsp_clock_cfg.h | 40 #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKA Div /4 */ macro
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| /bsp/renesas/ra6m3-ek/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 116 #define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKA_DIV)
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| A D | bsp_clocks.c | 131 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS ((BSP_CFG_PCLKA_DIV & 0x7U) << 12U)
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| /bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 116 #define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKA_DIV)
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| A D | bsp_clocks.c | 131 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS ((BSP_CFG_PCLKA_DIV & 0x7U) << 12U)
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| /bsp/renesas/ra6m4-iot/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 116 #define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKA_DIV)
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| A D | bsp_clocks.c | 131 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS ((BSP_CFG_PCLKA_DIV & 0x7U) << 12U)
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| /bsp/renesas/ra2l1-cpk/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 116 #define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKA_DIV)
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| A D | bsp_clocks.c | 131 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS ((BSP_CFG_PCLKA_DIV & 0x7U) << 12U)
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| /bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 133 #define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV)
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| /bsp/renesas/ra8m1-ek/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 133 #define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV)
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| /bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 133 #define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV)
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| /bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 133 #define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV)
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| /bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 133 #define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV)
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| /bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 133 #define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV)
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