| /bsp/renesas/ra2l1-cpk/ra_gen/ |
| A D | bsp_clock_cfg.h | 10 #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ macro
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| /bsp/renesas/ra6m3-ek/ra_gen/ |
| A D | bsp_clock_cfg.h | 14 #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ macro
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| /bsp/renesas/ra6m3-hmi-board/ra_gen/ |
| A D | bsp_clock_cfg.h | 14 #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ macro
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| /bsp/renesas/ra4m2-eco/ra_gen/ |
| A D | bsp_clock_cfg.h | 19 #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ macro
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| /bsp/renesas/ra6m4-cpk/ra_gen/ |
| A D | bsp_clock_cfg.h | 20 #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ macro
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| /bsp/renesas/ra6m4-iot/ra_gen/ |
| A D | bsp_clock_cfg.h | 20 #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ macro
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| /bsp/renesas/ra4e2-eco/ra_gen/ |
| A D | bsp_clock_cfg.h | 19 #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ macro
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| /bsp/renesas/ra6e2-fpb/ra_gen/ |
| A D | bsp_clock_cfg.h | 19 #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ macro
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| /bsp/renesas/ebf_qi_min_6m5/ra_gen/ |
| A D | bsp_clock_cfg.h | 23 #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ macro
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| /bsp/renesas/ra8m1-ek/ra_gen/ |
| A D | bsp_clock_cfg.h | 40 #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKB Div /8 */ macro
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| /bsp/renesas/ra8d1-ek/ra_gen/ |
| A D | bsp_clock_cfg.h | 41 #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKB Div /8 */ macro
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| /bsp/renesas/ra8d1-vision-board/ra_gen/ |
| A D | bsp_clock_cfg.h | 41 #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKB Div /8 */ macro
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| /bsp/renesas/ra6m3-ek/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 117 #define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKB_DIV)
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| A D | bsp_clocks.c | 126 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0x7U) << 8U)
140 #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0x7U) << 16U)
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| /bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 117 #define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKB_DIV)
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| A D | bsp_clocks.c | 126 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0x7U) << 8U)
140 #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0x7U) << 16U)
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| /bsp/renesas/ra6m4-iot/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 117 #define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKB_DIV)
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| A D | bsp_clocks.c | 126 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0x7U) << 8U)
140 #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0x7U) << 16U)
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| /bsp/renesas/ra2l1-cpk/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 117 #define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKB_DIV)
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| A D | bsp_clocks.c | 126 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0x7U) << 8U)
140 #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0x7U) << 16U)
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| /bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 161 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 8U)
175 #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 16U)
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| /bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 161 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 8U)
175 #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 16U)
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| /bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 164 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 8U)
178 #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 16U)
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| /bsp/renesas/ra8m1-ek/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 164 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 8U)
178 #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 16U)
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| /bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 164 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 8U)
178 #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 16U)
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