| /bsp/renesas/ra2l1-cpk/ra_gen/ |
| A D | bsp_clock_cfg.h | 11 #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ macro
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| /bsp/renesas/ra6m3-ek/ra_gen/ |
| A D | bsp_clock_cfg.h | 16 #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ macro
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| /bsp/renesas/ra6m3-hmi-board/ra_gen/ |
| A D | bsp_clock_cfg.h | 16 #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ macro
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| /bsp/renesas/ra4m2-eco/ra_gen/ |
| A D | bsp_clock_cfg.h | 21 #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ macro
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| /bsp/renesas/ra6m4-cpk/ra_gen/ |
| A D | bsp_clock_cfg.h | 22 #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ macro
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| /bsp/renesas/ra6m4-iot/ra_gen/ |
| A D | bsp_clock_cfg.h | 22 #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ macro
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| /bsp/renesas/ra4e2-eco/ra_gen/ |
| A D | bsp_clock_cfg.h | 21 #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ macro
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| /bsp/renesas/ra6e2-fpb/ra_gen/ |
| A D | bsp_clock_cfg.h | 21 #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ macro
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| /bsp/renesas/ebf_qi_min_6m5/ra_gen/ |
| A D | bsp_clock_cfg.h | 25 #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ macro
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| /bsp/renesas/ra8m1-ek/ra_gen/ |
| A D | bsp_clock_cfg.h | 42 #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKD Div /4 */ macro
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| /bsp/renesas/ra8d1-ek/ra_gen/ |
| A D | bsp_clock_cfg.h | 43 #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKD Div /4 */ macro
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| /bsp/renesas/ra8d1-vision-board/ra_gen/ |
| A D | bsp_clock_cfg.h | 43 #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKD Div /4 */ macro
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| /bsp/renesas/ra6m3-ek/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 119 #define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKD_DIV)
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| A D | bsp_clocks.c | 116 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (BSP_CFG_PCLKD_DIV & 0x7U)
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| /bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 119 #define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKD_DIV)
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| A D | bsp_clocks.c | 116 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (BSP_CFG_PCLKD_DIV & 0x7U)
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| /bsp/renesas/ra6m4-iot/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 119 #define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKD_DIV)
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| A D | bsp_clocks.c | 116 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (BSP_CFG_PCLKD_DIV & 0x7U)
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| /bsp/renesas/ra2l1-cpk/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 119 #define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKD_DIV)
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| A D | bsp_clocks.c | 116 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (BSP_CFG_PCLKD_DIV & 0x7U)
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| /bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 136 #define BSP_PRV_PCLKD_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV)
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| /bsp/renesas/ra8m1-ek/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 136 #define BSP_PRV_PCLKD_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV)
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| /bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 136 #define BSP_PRV_PCLKD_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV)
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| /bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 136 #define BSP_PRV_PCLKD_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV)
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| /bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.h | 136 #define BSP_PRV_PCLKD_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV)
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