BSP_CFG_PCLKE_DIV (reference) in projects: bsp

Searched refs:BSP_CFG_PCLKE_DIV (Results 1 – 19 of 19) sorted by relevance

/bsp/renesas/ra8m1-ek/ra_gen/
A D	bsp_clock_cfg.h	`43 #define BSP_CFG_PCLKE_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKE Div /2 */ macro`
/bsp/renesas/ra8d1-ek/ra_gen/
A D	bsp_clock_cfg.h	`44 #define BSP_CFG_PCLKE_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKE Div /2 */ macro`
/bsp/renesas/ra8d1-vision-board/ra_gen/
A D	bsp_clock_cfg.h	`44 #define BSP_CFG_PCLKE_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKE Div /2 */ macro`
/bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/mcu/all/
A D	bsp_clocks.h	`137 #define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV)`
A D	bsp_clocks.c	`149 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U)`
/bsp/renesas/ra8m1-ek/ra/fsp/src/bsp/mcu/all/
A D	bsp_clocks.h	`137 #define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV)`
A D	bsp_clocks.c	`149 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U)`
/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/mcu/all/
A D	bsp_clocks.h	`137 #define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV)`
A D	bsp_clocks.c	`149 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U)`
/bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/mcu/all/
A D	bsp_clocks.h	`137 #define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV)`
A D	bsp_clocks.c	`149 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U)`
/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/
A D	bsp_clocks.h	`137 #define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV)`
A D	bsp_clocks.c	`146 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U)`
/bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/
A D	bsp_clocks.h	`137 #define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV)`
A D	bsp_clocks.c	`146 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U)`
/bsp/renesas/ra4e2-eco/ra/fsp/src/bsp/mcu/all/
A D	bsp_clocks.h	`154 #define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV)`
A D	bsp_clocks.c	`185 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U)`
/bsp/renesas/ra6e2-fpb/ra/fsp/src/bsp/mcu/all/
A D	bsp_clocks.h	`155 #define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV)`
A D	bsp_clocks.c	`174 #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U)`

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