| /bsp/renesas/ra4m2-eco/ra_gen/ |
| A D | bsp_clock_cfg.h | 12 #define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ macro
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| /bsp/renesas/ra6m4-cpk/ra_gen/ |
| A D | bsp_clock_cfg.h | 12 #define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ macro
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| /bsp/renesas/ra6m4-iot/ra_gen/ |
| A D | bsp_clock_cfg.h | 12 #define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ macro
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| /bsp/renesas/ebf_qi_min_6m5/ra_gen/ |
| A D | bsp_clock_cfg.h | 12 #define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ macro
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| /bsp/renesas/ra8m1-ek/ra_gen/ |
| A D | bsp_clock_cfg.h | 19 #define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL2 Div /1 */ macro
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| /bsp/renesas/ra8d1-ek/ra_gen/ |
| A D | bsp_clock_cfg.h | 19 #define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL2 Div /1 */ macro
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| /bsp/renesas/ra8d1-vision-board/ra_gen/ |
| A D | bsp_clock_cfg.h | 19 #define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL2 Div /1 */ macro
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| /bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 317 BSP_CFG_PLL2_DIV)
328 … (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
1177 (BSP_CFG_PLL2_DIV + 1U); in bsp_clock_freq_var_init()
1184 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
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| /bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 199 (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
886 (BSP_CFG_PLL2_DIV + 1U); in bsp_clock_freq_var_init()
889 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
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| /bsp/renesas/ra6m4-iot/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 199 (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
886 (BSP_CFG_PLL2_DIV + 1U); in bsp_clock_freq_var_init()
889 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
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| /bsp/renesas/ra2l1-cpk/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 199 (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
886 (BSP_CFG_PLL2_DIV + 1U); in bsp_clock_freq_var_init()
889 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
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| /bsp/renesas/ra6m3-ek/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 199 (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
886 (BSP_CFG_PLL2_DIV + 1U); in bsp_clock_freq_var_init()
889 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
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| /bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 313 BSP_CFG_PLL2_DIV)
324 … (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
1183 (BSP_CFG_PLL2_DIV + 1U); in bsp_clock_freq_var_init()
1190 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
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| /bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 316 BSP_CFG_PLL2_DIV)
327 … (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
1375 (BSP_CFG_PLL2_DIV + 1U); in bsp_clock_freq_var_init()
1382 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
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| /bsp/renesas/ra8m1-ek/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 316 BSP_CFG_PLL2_DIV)
327 … (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
1353 (BSP_CFG_PLL2_DIV + 1U); in bsp_clock_freq_var_init()
1360 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
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| /bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 316 BSP_CFG_PLL2_DIV)
327 … (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
1375 (BSP_CFG_PLL2_DIV + 1U); in bsp_clock_freq_var_init()
1382 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
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| /bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 316 BSP_CFG_PLL2_DIV)
327 … (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
1375 (BSP_CFG_PLL2_DIV + 1U); in bsp_clock_freq_var_init()
1382 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
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| /bsp/renesas/ra6e2-fpb/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 383 BSP_CFG_PLL2_DIV)
394 … (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
1939 (BSP_CFG_PLL2_DIV + 1U); in bsp_clock_freq_var_init()
1946 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
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| /bsp/renesas/ra4e2-eco/ra/fsp/src/bsp/mcu/all/ |
| A D | bsp_clocks.c | 394 BSP_CFG_PLL2_DIV)
405 … (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \
2072 (BSP_CFG_PLL2_DIV + 1U); in bsp_clock_freq_var_init()
2079 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
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