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Searched refs:BSP_CFG_PLL2_MUL (Results 1 – 19 of 19) sorted by relevance

/bsp/renesas/ra4m2-eco/ra_gen/
A Dbsp_clock_cfg.h13 #define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */ macro
/bsp/renesas/ra6m4-cpk/ra_gen/
A Dbsp_clock_cfg.h13 #define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL2 Mul x20.0 */ macro
/bsp/renesas/ra6m4-iot/ra_gen/
A Dbsp_clock_cfg.h13 #define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL2 Mul x20.0 */ macro
/bsp/renesas/ebf_qi_min_6m5/ra_gen/
A Dbsp_clock_cfg.h13 #define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */ macro
/bsp/renesas/ra8m1-ek/ra_gen/
A Dbsp_clock_cfg.h20 #define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(48,0) /* PLL2 Mul x40-59|Mul x48|PLL2 Mul x48.00 */ macro
/bsp/renesas/ra8d1-ek/ra_gen/
A Dbsp_clock_cfg.h20 #define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(48,0) /* PLL2 Mul x40-59|Mul x48|PLL2 Mul x48.00 */ macro
/bsp/renesas/ra8d1-vision-board/ra_gen/
A Dbsp_clock_cfg.h20 #define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(48,0) /* PLL2 Mul x40-59|Mul x48|PLL2 Mul x48.00 */ macro
/bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c314 …#define BSP_PRV_PLL2CCR ((((BSP_CFG_PLL2_MUL & BSP_PRV_PLL2_MUL_CFG_MA…
327 …#define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL…
1176 …_CLOCKS_SOURCE_CLOCK_PLL2] = ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
1184 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c198 #define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL_Pos) | \
885 …_CLOCKS_SOURCE_CLOCK_PLL2] = ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
889 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
/bsp/renesas/ra6m4-iot/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c198 #define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL_Pos) | \
885 …_CLOCKS_SOURCE_CLOCK_PLL2] = ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
889 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
/bsp/renesas/ra2l1-cpk/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c198 #define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL_Pos) | \
885 …_CLOCKS_SOURCE_CLOCK_PLL2] = ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
889 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
/bsp/renesas/ra6m3-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c198 #define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL_Pos) | \
885 …_CLOCKS_SOURCE_CLOCK_PLL2] = ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
889 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c310 …#define BSP_PRV_PLL2CCR ((((BSP_CFG_PLL2_MUL & BSP_PRV_PLL2_MUL_CFG_MA…
323 …#define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL…
1182 …_CLOCKS_SOURCE_CLOCK_PLL2] = ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
1190 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
/bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c313 …#define BSP_PRV_PLL2CCR ((((BSP_CFG_PLL2_MUL & BSP_PRV_PLL2_MUL_CFG_MA…
326 …#define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL…
1374 …_CLOCKS_SOURCE_CLOCK_PLL2] = ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
1382 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
/bsp/renesas/ra8m1-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c313 …#define BSP_PRV_PLL2CCR ((((BSP_CFG_PLL2_MUL & BSP_PRV_PLL2_MUL_CFG_MA…
326 …#define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL…
1352 …_CLOCKS_SOURCE_CLOCK_PLL2] = ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
1360 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
/bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c313 …#define BSP_PRV_PLL2CCR ((((BSP_CFG_PLL2_MUL & BSP_PRV_PLL2_MUL_CFG_MA…
326 …#define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL…
1374 …_CLOCKS_SOURCE_CLOCK_PLL2] = ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
1382 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c313 …#define BSP_PRV_PLL2CCR ((((BSP_CFG_PLL2_MUL & BSP_PRV_PLL2_MUL_CFG_MA…
326 …#define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL…
1374 …_CLOCKS_SOURCE_CLOCK_PLL2] = ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
1382 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
/bsp/renesas/ra6e2-fpb/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c380 …#define BSP_PRV_PLL2CCR ((((BSP_CFG_PLL2_MUL & BSP_PRV_PLL2_MUL_CFG_MA…
393 …#define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL…
1938 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) / in bsp_clock_freq_var_init()
1946 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()
/bsp/renesas/ra4e2-eco/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c391 …#define BSP_PRV_PLL2CCR ((((BSP_CFG_PLL2_MUL & BSP_PRV_PLL2_MUL_CFG_MA…
404 …#define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL…
2071 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) / in bsp_clock_freq_var_init()
2079 ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; in bsp_clock_freq_var_init()

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