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Searched refs:BSP_CFG_PLL_MUL (Results 1 – 25 of 35) sorted by relevance

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/bsp/renesas/ra6m3-ek/ra_gen/
A Dbsp_clock_cfg.h10 #define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */ macro
/bsp/renesas/ra6m3-hmi-board/ra_gen/
A Dbsp_clock_cfg.h10 #define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL Mul x20.0 */ macro
/bsp/renesas/ra4m2-eco/ra_gen/
A Dbsp_clock_cfg.h10 #define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */ macro
/bsp/renesas/ra6m3-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.h104 …#define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U…
108 …#define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U…
/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.h104 …#define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U…
108 …#define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U…
A Dbsp_clocks.c177 #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \
186 #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1)
874 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
877 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
/bsp/renesas/ra6m4-iot/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.h104 …#define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U…
108 …#define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U…
A Dbsp_clocks.c177 #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \
186 #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1)
874 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
877 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
/bsp/renesas/ra2l1-cpk/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.h104 …#define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U…
108 …#define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U…
/bsp/renesas/ra6m4-cpk/ra_gen/
A Dbsp_clock_cfg.h10 #define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */ macro
/bsp/renesas/ra6m4-iot/ra_gen/
A Dbsp_clock_cfg.h10 #define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_25_0 /* PLL Mul x25.0 */ macro
/bsp/renesas/ra4e2-eco/ra_gen/
A Dbsp_clock_cfg.h10 #define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(10,0) /* PLL Mul x10.0 */ macro
/bsp/renesas/ra6e2-fpb/ra_gen/
A Dbsp_clock_cfg.h10 #define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(10,0) /* PLL Mul x10.0 */ macro
/bsp/renesas/ebf_qi_min_6m5/ra_gen/
A Dbsp_clock_cfg.h10 #define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */ macro
/bsp/renesas/ra8m1-ek/ra_gen/
A Dbsp_clock_cfg.h10 #define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(48,0) /* PLL Mul x40-59|Mul x48|PLL Mul x48.00 */ macro
/bsp/renesas/ra8d1-ek/ra_gen/
A Dbsp_clock_cfg.h10 #define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(48,0) /* PLL Mul x40-59|Mul x48|PLL Mul x48.00 */ macro
/bsp/renesas/ra8d1-vision-board/ra_gen/
A Dbsp_clock_cfg.h10 #define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(48,0) /* PLL Mul x40-59|Mul x48|PLL Mul x48.00 */ macro
/bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c232 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK)…
247 #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1)
265 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLL_MUL_CFG_MACRO_P…
290 …#define BSP_PRV_PLLCCR (((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) …
1159 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
1166 …q[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U; in bsp_clock_freq_var_init()
1168 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c232 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK)…
247 #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1)
265 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLL_MUL_CFG_MACRO_P…
288 …#define BSP_PRV_PLLCCR (((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) …
1165 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
1172 …q[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U; in bsp_clock_freq_var_init()
1174 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
/bsp/renesas/ra6e2-fpb/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c271 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK)…
286 #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1)
304 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLL_MUL_CFG_MACRO_P…
327 …#define BSP_PRV_PLLCCR (((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) …
346 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) …
351 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) …
356 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) …
1919 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
1926 …q[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U; in bsp_clock_freq_var_init()
1929 ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) >> in bsp_clock_freq_var_init()
/bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c235 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK)…
250 #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1)
268 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLL_MUL_CFG_MACRO_P…
291 …#define BSP_PRV_PLLCCR (((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) …
1357 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
1364 …q[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U; in bsp_clock_freq_var_init()
1366 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
/bsp/renesas/ra8m1-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c235 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK)…
250 #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1)
268 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLL_MUL_CFG_MACRO_P…
291 …#define BSP_PRV_PLLCCR (((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) …
1335 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
1342 …q[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U; in bsp_clock_freq_var_init()
1344 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
/bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c235 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK)…
250 #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1)
268 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLL_MUL_CFG_MACRO_P…
291 …#define BSP_PRV_PLLCCR (((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) …
1357 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
1364 …q[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U; in bsp_clock_freq_var_init()
1366 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c235 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK)…
250 #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1)
268 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLL_MUL_CFG_MACRO_P…
291 …#define BSP_PRV_PLLCCR (((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) …
1357 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
1364 …q[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U; in bsp_clock_freq_var_init()
1366 …BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U)… in bsp_clock_freq_var_init()
/bsp/renesas/ra4e2-eco/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c282 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK)…
297 #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1)
315 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLL_MUL_CFG_MACRO_P…
338 …#define BSP_PRV_PLLCCR (((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) …
357 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) …
362 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) …
367 …#define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) …
2051 ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) / in bsp_clock_freq_var_init()
2058 …_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> in bsp_clock_freq_var_init()
2062 ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) >> in bsp_clock_freq_var_init()

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