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Searched refs:BSP_CFG_PLODIVQ (Results 1 – 11 of 11) sorted by relevance

/bsp/renesas/ra8m1-ek/ra_gen/
A Dbsp_clock_cfg.h14 #define BSP_CFG_PLODIVQ (BSP_CLOCKS_PLL_DIV_2) /* PLL1Q Div /2 */ macro
/bsp/renesas/ra8d1-ek/ra_gen/
A Dbsp_clock_cfg.h14 #define BSP_CFG_PLODIVQ (BSP_CLOCKS_PLL_DIV_4) /* PLL1Q Div /4 */ macro
/bsp/renesas/ra8d1-vision-board/ra_gen/
A Dbsp_clock_cfg.h14 #define BSP_CFG_PLODIVQ (BSP_CLOCKS_PLL_DIV_4) /* PLL1Q Div /4 */ macro
/bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c274 … ((BSP_CFG_PLODIVQ & BSP_PRV_PLLCCR2_PLL_DIV_MASK) << \
/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c274 … ((BSP_CFG_PLODIVQ & BSP_PRV_PLLCCR2_PLL_DIV_MASK) << \
/bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c277 … ((BSP_CFG_PLODIVQ & BSP_PRV_PLLCCR2_PLL_DIV_MASK) << \
/bsp/renesas/ra8m1-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c277 … ((BSP_CFG_PLODIVQ & BSP_PRV_PLLCCR2_PLL_DIV_MASK) << \
/bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c277 … ((BSP_CFG_PLODIVQ & BSP_PRV_PLLCCR2_PLL_DIV_MASK) << \
/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c277 … ((BSP_CFG_PLODIVQ & BSP_PRV_PLLCCR2_PLL_DIV_MASK) << \
/bsp/renesas/ra6e2-fpb/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c313 … ((BSP_CFG_PLODIVQ & BSP_PRV_PLLCCR2_PLL_DIV_MASK) << \
/bsp/renesas/ra4e2-eco/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.c324 … ((BSP_CFG_PLODIVQ & BSP_PRV_PLLCCR2_PLL_DIV_MASK) << \

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