BSP_CFG_SCI5ASYNCCLK (reference) in projects: bsp

Searched refs:BSP_CFG_SCI5ASYNCCLK (Results 1 – 6 of 6) sorted by relevance

/bsp/renesas/rzn2l_etherkit/rzn_gen/
A D	bsp_clock_cfg.h	`34 #define BSP_CFG_SCI5ASYNCCLK (BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI5ASYNCCLK: 96… macro`
/bsp/renesas/rzn2l_rsk/rzn_gen/
A D	bsp_clock_cfg.h	`34 #define BSP_CFG_SCI5ASYNCCLK (BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI5ASYNCCLK: 96… macro`
/bsp/renesas/rzt2m_rsk/rzt_gen/
A D	bsp_clock_cfg.h	`32 #define BSP_CFG_SCI5ASYNCCLK (BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI5ASYNCCLK: 96… macro`
/bsp/renesas/rzn2l_etherkit/rzn/fsp/src/bsp/mcu/all/
A D	bsp_clocks.c	`59 #define BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS ((BSP_CFG_SCI5ASYNCCLK & 1U) << 25U)`
/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/
A D	bsp_clocks.c	`59 #define BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS ((BSP_CFG_SCI5ASYNCCLK & 1U) << 25U)`
/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/
A D	bsp_clocks.c	`64 #define BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS ((BSP_CFG_SCI5ASYNCCLK & 1U) << 25U)`

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