BSP_CFG_SPI2ASYNCCLK (reference) in projects: bsp

Searched refs:BSP_CFG_SPI2ASYNCCLK (Results 1 – 6 of 6) sorted by relevance

/bsp/renesas/rzn2l_etherkit/rzn_gen/
A D	bsp_clock_cfg.h	`37 #define BSP_CFG_SPI2ASYNCCLK (BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI2ASYNCCLK: 96… macro`
/bsp/renesas/rzn2l_rsk/rzn_gen/
A D	bsp_clock_cfg.h	`37 #define BSP_CFG_SPI2ASYNCCLK (BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI2ASYNCCLK: 96… macro`
/bsp/renesas/rzt2m_rsk/rzt_gen/
A D	bsp_clock_cfg.h	`35 #define BSP_CFG_SPI2ASYNCCLK (BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI2ASYNCCLK: 96… macro`
/bsp/renesas/rzn2l_etherkit/rzn/fsp/src/bsp/mcu/all/
A D	bsp_clocks.c	`47 #define BSP_PRV_STARTUP_SCKCR_SPI2ASYNCSEL_BITS ((BSP_CFG_SPI2ASYNCCLK & 1U) << 26U)`
/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/
A D	bsp_clocks.c	`47 #define BSP_PRV_STARTUP_SCKCR_SPI2ASYNCSEL_BITS ((BSP_CFG_SPI2ASYNCCLK & 1U) << 26U)`
/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/
A D	bsp_clocks.c	`47 #define BSP_PRV_STARTUP_SCKCR_SPI2ASYNCSEL_BITS ((BSP_CFG_SPI2ASYNCCLK & 1U) << 26U)`

Completed in 7 milliseconds