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Searched refs:BSP_CFG_XTAL_HZ (Results 1 – 25 of 48) sorted by relevance

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/bsp/renesas/ra6m3-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.h71 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
78 #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
96 #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ)
100 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
107 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.h71 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
78 #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
96 #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ)
100 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
107 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
/bsp/renesas/ra6m4-iot/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.h71 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
78 #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
96 #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ)
100 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
107 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
/bsp/renesas/ra2l1-cpk/ra/fsp/src/bsp/mcu/all/
A Dbsp_clocks.h71 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
78 #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
96 #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ)
100 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
107 #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
/bsp/renesas/ra6m3-ek/ra/fsp/src/bsp/mcu/ra6m3/
A Dbsp_feature.h33 #if (BSP_CFG_XTAL_HZ > (19999999))
35 #elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000))
37 #elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000))
/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/mcu/ra6m4/
A Dbsp_feature.h33 #if (BSP_CFG_XTAL_HZ > (19999999))
35 #elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000))
37 #elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000))
/bsp/renesas/ra6m4-iot/ra/fsp/src/bsp/mcu/ra6m4/
A Dbsp_feature.h33 #if (BSP_CFG_XTAL_HZ > (19999999))
35 #elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000))
37 #elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000))
/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/mcu/ra6m5/
A Dbsp_feature.h33 #if (BSP_CFG_XTAL_HZ > (19999999))
35 #elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000))
37 #elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000))
/bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/mcu/ra4m2/
A Dbsp_feature.h33 #if (BSP_CFG_XTAL_HZ > (19999999))
35 #elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000))
37 #elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000))
/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/mcu/ra6m3/
A Dbsp_feature.h33 #if (BSP_CFG_XTAL_HZ > (19999999))
35 #elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000))
37 #elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000))
/bsp/renesas/ra6e2-fpb/ra/fsp/src/bsp/mcu/ra6e2/
A Dbsp_feature.h20 #if (BSP_CFG_XTAL_HZ > (19999999))
22 #elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000))
24 #elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000))
/bsp/renesas/ra2l1-cpk/ra_gen/
A Dbsp_clock_cfg.h6 #define BSP_CFG_XTAL_HZ (20000000) /* XTAL 20000000Hz */ macro
/bsp/renesas/ra8m1-ek/ra/fsp/src/bsp/mcu/ra8m1/
A Dbsp_feature.h33 #if (BSP_CFG_XTAL_HZ > (24000000))
35 #elif (BSP_CFG_XTAL_HZ > (8000000)) && (BSP_CFG_XTAL_HZ <= (24000000))
/bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/mcu/ra8d1/
A Dbsp_feature.h34 #if (BSP_CFG_XTAL_HZ > (24000000))
36 #elif (BSP_CFG_XTAL_HZ > (8000000)) && (BSP_CFG_XTAL_HZ <= (24000000))
/bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/mcu/ra8d1/
A Dbsp_feature.h34 #if (BSP_CFG_XTAL_HZ > (24000000))
36 #elif (BSP_CFG_XTAL_HZ > (8000000)) && (BSP_CFG_XTAL_HZ <= (24000000))
/bsp/renesas/ra6m3-ek/ra_gen/
A Dbsp_clock_cfg.h6 #define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ macro
/bsp/renesas/ra6m3-hmi-board/ra_gen/
A Dbsp_clock_cfg.h6 #define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ macro
/bsp/renesas/ra4m2-eco/ra_gen/
A Dbsp_clock_cfg.h6 #define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ macro
/bsp/renesas/ra6m4-cpk/ra_gen/
A Dbsp_clock_cfg.h6 #define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ macro
/bsp/renesas/ra6m4-iot/ra_gen/
A Dbsp_clock_cfg.h6 #define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ macro
/bsp/renesas/ra4e2-eco/ra_gen/
A Dbsp_clock_cfg.h6 #define BSP_CFG_XTAL_HZ (20000000) /* XTAL 20000000Hz */ macro
/bsp/renesas/ra6e2-fpb/ra_gen/
A Dbsp_clock_cfg.h6 #define BSP_CFG_XTAL_HZ (20000000) /* XTAL 20000000Hz */ macro
/bsp/renesas/ebf_qi_min_6m5/ra_gen/
A Dbsp_clock_cfg.h6 #define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ macro
/bsp/renesas/ra8m1-ek/ra_gen/
A Dbsp_clock_cfg.h6 #define BSP_CFG_XTAL_HZ (20000000) /* XTAL 20000000Hz */ macro
/bsp/renesas/ra8d1-ek/ra_gen/
A Dbsp_clock_cfg.h6 #define BSP_CFG_XTAL_HZ (20000000) /* XTAL 20000000Hz */ macro

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