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Searched refs:BSP_PRV_SDRAM_CL (Results 1 – 4 of 4) sorted by relevance

/bsp/renesas/ra8d1-vision-board/ra/board/ra8d1_ek/
A Dboard_sdram.c71 #define BSP_PRV_SDRAM_CL (3U) macro
218 (uint16_t) (BSP_PRV_SDRAM_CL << 4)) | in bsp_sdram_init()
233 R_BUS->SDRAM.SDTR_b.CL = BSP_PRV_SDRAM_CL; /* set SDRAM column latency cycles */ in bsp_sdram_init()
/bsp/renesas/ra8d1-ek/ra/board/ra8d1_ek/
A Dboard_sdram.c71 #define BSP_PRV_SDRAM_CL (3U) macro
218 (uint16_t) (BSP_PRV_SDRAM_CL << 4)) | in bsp_sdram_init()
233 R_BUS->SDRAM.SDTR_b.CL = BSP_PRV_SDRAM_CL; /* set SDRAM column latency cycles */ in bsp_sdram_init()
/bsp/renesas/ra8d1-vision-board/board/ports/
A Ddrv_sdram.c68 #define BSP_PRV_SDRAM_CL (3U) macro
215 (uint16_t)(BSP_PRV_SDRAM_CL << 4)) | in drv_sdram_init()
230 R_BUS->SDRAM.SDTR_b.CL = BSP_PRV_SDRAM_CL; /* set SDRAM column latency cycles */ in drv_sdram_init()
/bsp/renesas/ra8d1-ek/board/ports/
A Ddrv_sdram.c60 #define BSP_PRV_SDRAM_CL (3U) macro
207 (uint16_t) (BSP_PRV_SDRAM_CL << 4)) | in drv_sdram_init()
222 R_BUS->SDRAM.SDTR_b.CL = BSP_PRV_SDRAM_CL; /* set SDRAM column latency cycles */ in drv_sdram_init()

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