BSP_PRV_SDRAM_TRCD (reference) in projects: bsp

Searched refs:BSP_PRV_SDRAM_TRCD (Results 1 – 4 of 4) sorted by relevance

/bsp/renesas/ra8d1-vision-board/ra/board/ra8d1_ek/
A D	board_sdram.c	`50 #define BSP_PRV_SDRAM_TRCD (3U) macro 230 R_BUS->SDRAM.SDTR_b.RCD = BSP_PRV_SDRAM_TRCD - 1U; /* set ACTIVE to READ/WRITE delay cycles */ in bsp_sdram_init()`
/bsp/renesas/ra8d1-ek/ra/board/ra8d1_ek/
A D	board_sdram.c	`50 #define BSP_PRV_SDRAM_TRCD (3U) macro 230 R_BUS->SDRAM.SDTR_b.RCD = BSP_PRV_SDRAM_TRCD - 1U; /* set ACTIVE to READ/WRITE delay cycles */ in bsp_sdram_init()`
/bsp/renesas/ra8d1-vision-board/board/ports/
A D	drv_sdram.c	`47 #define BSP_PRV_SDRAM_TRCD (3U) macro 227 R_BUS->SDRAM.SDTR_b.RCD = BSP_PRV_SDRAM_TRCD - 1U; /* set ACTIVE to READ/WRITE delay cycles */ in drv_sdram_init()`
/bsp/renesas/ra8d1-ek/board/ports/
A D	drv_sdram.c	`39 #define BSP_PRV_SDRAM_TRCD (3U) macro 219 R_BUS->SDRAM.SDTR_b.RCD = BSP_PRV_SDRAM_TRCD - 1U; /* set ACTIVE to READ/WRITE delay cycles */ in drv_sdram_init()`

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