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Searched refs:Bank (Results 1 – 25 of 40) sorted by relevance

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/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/
A Dxgpiops_intr.c110 u8 Bank; in XGpioPs_IntrEnablePin() local
183 u8 Bank; in XGpioPs_IntrDisablePin() local
261 u8 Bank; in XGpioPs_IntrGetEnabledPin() local
334 u8 Bank; in XGpioPs_IntrGetStatusPin() local
407 u8 Bank; in XGpioPs_IntrClearPin() local
561 u8 Bank; in XGpioPs_SetIntrTypePin() local
649 u8 Bank; in XGpioPs_GetIntrTypePin() local
751 u8 Bank; in XGpioPs_IntrHandler() local
758 for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) { in XGpioPs_IntrHandler()
765 if((Bank == XGPIOPS_ONE) || (Bank == XGPIOPS_TWO)) { in XGpioPs_IntrHandler()
[all …]
A Dxgpiops.c210 Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); in XGpioPs_Read()
237 u8 Bank; in XGpioPs_ReadPin() local
281 Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); in XGpioPs_Write()
311 u8 Bank; in XGpioPs_WritePin() local
376 Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); in XGpioPs_SetDirection()
401 u8 Bank; in XGpioPs_SetDirectionPin() local
455 Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); in XGpioPs_GetDirection()
483 u8 Bank; in XGpioPs_GetDirectionPin() local
530 Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); in XGpioPs_SetOutputEnable()
559 u8 Bank; in XGpioPs_SetOutputEnablePin() local
[all …]
A Dxgpiops.h177 typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
212 u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank);
213 void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data);
215 u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank);
217 u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank);
237 void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
238 void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
239 u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
240 u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
241 void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
[all …]
/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/
A Dn32g45x_xfmc.c130 assert_param(IS_XFMC_NAND_BANK(Bank)); in XFMC_DeInitNand()
132 Bank->CTRLx = XFMC_NAND_CTRL_RESET; in XFMC_DeInitNand()
133 Bank->STSx = XFMC_NAND_STS_RESET; in XFMC_DeInitNand()
134 Bank->CMEMTMx = XFMC_NAND_CMEMTM_RESET; in XFMC_DeInitNand()
376 assert_param(IS_XFMC_NAND_BANK(Bank)); in XFMC_EnableNand()
403 assert_param(IS_XFMC_NAND_BANK(Bank)); in XFMC_EnableNandEcc()
428 Bank->CTRLx &= ~XFMC_NAND_ECC_ENABLE; in XFMC_RestartNandEcc()
429 Bank->CTRLx |= XFMC_NAND_ECC_ENABLE; in XFMC_RestartNandEcc()
444 assert_param(IS_XFMC_NAND_BANK(Bank)); in XFMC_GetEcc()
492 assert_param(IS_XFMC_NAND_BANK(Bank)); in XFMC_GetFlag()
[all …]
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/
A Dstm32l1xx_ll_fsmc.c244 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); in FSMC_NORSRAM_DeInit()
247 __FSMC_NORSRAM_DISABLE(Device, Bank); in FSMC_NORSRAM_DeInit()
251 if (Bank == FSMC_NORSRAM_BANK1) in FSMC_NORSRAM_DeInit()
253 Device->BTCR[Bank] = 0x000030DBU; in FSMC_NORSRAM_DeInit()
258 Device->BTCR[Bank] = 0x000030D2U; in FSMC_NORSRAM_DeInit()
261 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
262 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
288 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); in FSMC_NORSRAM_Timing_Init()
342 Device->BWTR[Bank] = 0x0FFFFFFFU; in FSMC_NORSRAM_Extended_Timing_Init()
376 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); in FSMC_NORSRAM_WriteOperation_Enable()
[all …]
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_ll_fsmc.h489 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
491 … FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
494 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
502 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
503 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/
A Dn32g45x_xfmc.h196 XFMC_Bank23_Module *Bank; /*!< Specifies the NAND memory bank that will be used. member
793 void XFMC_DeInitNand(XFMC_Bank23_Module *Bank);
799 void XFMC_EnableNand(XFMC_Bank23_Module *Bank, FunctionalState Cmd);
800 void XFMC_EnableNandEcc(XFMC_Bank23_Module *Bank, FunctionalState Cmd);
801 void XFMC_RestartNandEcc(XFMC_Bank23_Module *Bank);
802 uint32_t XFMC_GetEcc(XFMC_Bank23_Module *Bank);
803 FlagStatus XFMC_GetFlag(XFMC_Bank23_Module *Bank, uint32_t XFMC_FLAG);
804 void XFMC_ClrFlag(XFMC_Bank23_Module *Bank, uint32_t XFMC_FLAG);
/bsp/stm32/stm32h750-weact-ministm32h7xx/board/CubeMX_Config/
A DCubeMX_Config.ioc54 PE2.Mode=Single Bank 1
59 PB6.Mode=Single Bank 1
168 PD13.Mode=Single Bank 1
215 PD12.Mode=Single Bank 1
222 PB2.Mode=Single Bank 1
229 PD11.Mode=Single Bank 1
/bsp/stm32/stm32h750-fk750m1-vbt6/board/CubeMX_Config/
A DCubeMX_Config.ioc104 PB2.Mode=Single Bank 1
109 PB6.Mode=Single Bank 1
139 PD11.Mode=Single Bank 1
143 PD12.Mode=Single Bank 1
148 PD13.Mode=Single Bank 1
180 PE2.Mode=Single Bank 1
/bsp/stm32/stm32h750-armfly-h7-tool/board/CubeMX_Config/
A DCubeMX_Config.ioc137 PB2.Mode=Single Bank 1
180 PD11.Mode=Single Bank 1
183 PD12.Mode=Single Bank 1
186 PD13.Mode=Single Bank 1
195 PF7.Mode=Single Bank 1
207 PG6.Mode=Single Bank 1
/bsp/stm32/stm32l431-tencentos-tiny-EVB_MX+/board/CubeMX_Config/
A DCubeMX_Config.ioc99 PA3.Mode=Single Bank 1 2IOs
106 PB0.Mode=Single Bank 1 2IOs
108 PB1.Mode=Single Bank 1 2IOs
112 PB11.Mode=Single Bank 1 2IOs
/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/
A DSTM32L475VE.ioc196 PE10.Mode=Single Bank
198 PE11.Mode=Single Bank
201 PE12.Mode=Single Bank
204 PE13.Mode=Single Bank
207 PE14.Mode=Single Bank
210 PE15.Mode=Single Bank
/bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/
A DCubeMX_Config.ioc153 PB2.Mode=Single Bank 1
155 PB6.Mode=Single Bank 1
192 PD11.Mode=Single Bank 1
195 PD12.Mode=Single Bank 1
198 PD13.Mode=Single Bank 1
213 PE2.Mode=Single Bank 1
/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/
A DCubeMX_Config.ioc182 PB2.Mode=Single Bank 1
185 PB6.Mode=Single Bank 1
276 PF6.Mode=Single Bank 1
279 PF7.Mode=Single Bank 1
281 PF8.Mode=Single Bank 1
283 PF9.Mode=Single Bank 1
/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/libs/TARGET_CY8CKIT-062-WIFI-BT/config/GeneratedSource/
A Dqspi_config.cfg5 # This file contains a SMIF Bank layout for use with OpenOCD.
/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/config/GeneratedSource/
A Dqspi_config.cfg5 # This file contains a SMIF Bank layout for use with OpenOCD.
/bsp/Infineon/psoc6-cy8ckit-062s4/libs/TARGET_CY8CKIT-062S4/config/GeneratedSource/
A Dqspi_config.cfg5 # This file contains a SMIF Bank layout for use with OpenOCD.
/bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/config/GeneratedSource/
A Dqspi_config.cfg5 # This file contains a SMIF Bank layout for use with OpenOCD.
/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/config/GeneratedSource/
A Dqspi_config.cfg5 # This file contains a SMIF Bank layout for use with OpenOCD.
/bsp/Infineon/libraries/templates/XMC7200D/libs/TARGET_APP_KIT_XMC72_EVK/config/GeneratedSource/
A Dqspi_config.cfg5 # This file contains a SMIF Bank layout for use with OpenOCD.
/bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/config/GeneratedSource/
A Dqspi_config.cfg5 # This file contains a SMIF Bank layout for use with OpenOCD.
/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/config/GeneratedSource/
A Dqspi_config.cfg5 # This file contains a SMIF Bank layout for use with OpenOCD.
/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/
A Dqspi_config.cfg5 # This file contains a SMIF Bank layout for use with OpenOCD.
/bsp/Infineon/xmc7200-kit_xmc7200_evk/libs/TARGET_APP_KIT_XMC72_EVK/config/GeneratedSource/
A Dqspi_config.cfg5 # This file contains a SMIF Bank layout for use with OpenOCD.
/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/
A DCubeMX_Config.ioc209 PB2.Mode=Single Bank 1
212 PB6.Mode=Single Bank 1
287 PF6.Mode=Single Bank 1
290 PF7.Mode=Single Bank 1
293 PF8.Mode=Single Bank 1
296 PF9.Mode=Single Bank 1

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