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Searched refs:BaseAddr (Results 1 – 17 of 17) sorted by relevance

/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/
A Dxemacps_hw.c61 void XEmacPs_ResetHw(u32 BaseAddr) in XEmacPs_ResetHw() argument
66 XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U); in XEmacPs_ResetHw()
69 RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET); in XEmacPs_ResetHw()
77 XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal); in XEmacPs_ResetHw()
79 XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK); in XEmacPs_ResetHw()
81 XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK| in XEmacPs_ResetHw()
85 XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET, in XEmacPs_ResetHw()
88 XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U); in XEmacPs_ResetHw()
90 XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U); in XEmacPs_ResetHw()
94 XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U); in XEmacPs_ResetHw()
[all …]
A Dxemacps_hw.h639 void XEmacPs_ResetHw(u32 BaseAddr);
/bsp/ft2004/libraries/bsp/ft_i2c/
A Dft_i2c.c54 void FI2C_resetReg(u32 BaseAddr) in FI2C_resetReg() argument
78 FI2C_WriteReg(BaseAddr, SclLcntAddr, SclLcnt); in FI2C_setSclClk()
79 FI2C_WriteReg(BaseAddr, SclHcntAddr, SclHcnt); in FI2C_setSclClk()
92 FI2C_WriteReg(BaseAddr, I2C_CON, RegVal); in FI2C_setCtrlParam()
207 u32 RegVal = FI2C_ReadReg(BaseAddr, I2C_CON); in FI2C_sendRestartCmd()
209 FI2C_WriteReg(BaseAddr, I2C_CON, RegVal); in FI2C_sendRestartCmd()
215 FI2C_WriteReg(BaseAddr, I2C_TAR, RegVal); in FI2C_setTarAddr()
221 FI2C_WriteReg(BaseAddr, I2C_DATA_CMD, RegVal); in FI2C_sendWriteCmd()
228 FI2C_WriteReg(BaseAddr, I2C_DATA_CMD, RegVal); in FI2C_sendStartReadCmd()
231 void FI2C_sendStopCmd(FT_IN u32 BaseAddr) in FI2C_sendStopCmd() argument
[all …]
A Dft_i2c_hw.h315 void FI2C_resetReg(u32 BaseAddr);
/bsp/ft2004/libraries/bsp/ft_can/
A Dft_can_hw.h133 #define FCan_ReadReg(BaseAddr, RegOffset) \ argument
134 Ft_in32((BaseAddr) + (u32)(RegOffset))
150 #define FCan_WriteReg(BaseAddr, RegOffset, Data) \ argument
151 Ft_out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
153 #define FCan_SetBit(BaseAddr, RegOffset, Data) \ argument
154 Ft_setBit32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
156 #define FCan_ClearBit(BaseAddr, RegOffset, Data) \ argument
157 Ft_clearBit32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/
A Dxgpiops_intr.c89 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_IntrEnable()
126 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_IntrEnablePin()
162 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_IntrDisable()
199 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_IntrDisablePin()
387 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_IntrClear()
428 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_IntrClearPin()
475 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_SetIntrType()
479 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_SetIntrType()
483 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_SetIntrType()
616 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_SetIntrTypePin()
[all …]
A Dxgpiops.c90 InstancePtr->GpioConfig.BaseAddr = EffectiveAddr; in XGpioPs_CfgInitialize()
174 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_CfgInitialize()
214 return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_Read()
250 return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_ReadPin()
285 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_Write()
340 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_WritePin()
380 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_SetDirection()
426 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_SetDirectionPin()
459 return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_GetDirection()
534 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, in XGpioPs_SetOutputEnable()
[all …]
A Dxgpiops_hw.h117 #define XGpioPs_ReadReg(BaseAddr, RegOffset) \ argument
118 Xil_In32((BaseAddr) + (u32)(RegOffset))
134 #define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \ argument
135 Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
A Dxgpiops.h184 u32 BaseAddr; /**< Register base address */ member
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/
A Dstm32l1xx_ll_usb.c782 uint32_t BaseAddr = (uint32_t)USBx; in USB_WritePMA() local
787 pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); in USB_WritePMA()
816 uint32_t BaseAddr = (uint32_t)USBx; in USB_ReadPMA() local
821 pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); in USB_ReadPMA()
/bsp/zynqmp-r5-axu4ev/drivers/
A Ddrv_gpio.c80 ConfigPtr->BaseAddr) == XST_SUCCESS) in rt_hw_pin_init()
/bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Inc/
A Dhal_tim_32b.h431 TIM_32B_DMABurstBaseAddr_Type BaseAddr; /*!< The base address to start transfer. */ member
A Dhal_tim_16b.h433 TIM_16B_DMABurstBaseAddr_Type BaseAddr; /*!< The base address to start transfer. */ member
A Dhal_tim_adv.h461 TIM_ADV_DMABurstBaseAddr_Type BaseAddr; /*!< The base address to start transfer. */ member
/bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/
A Dhal_tim_16b.c280 TIMx->DCR = TIM_16B_DCR_DBA(conf->BaseAddr) | TIM_16B_DCR_DBL(conf->Length); in TIM_16B_EnableDMABurst()
A Dhal_tim_32b.c280 TIMx->DCR = TIM_32B_DCR_DBA(conf->BaseAddr) | TIM_32B_DCR_DBL(conf->Length); in TIM_32B_EnableDMABurst()
A Dhal_tim_adv.c321 TIMx->DCR = TIM_ADV_DCR_DBA(conf->BaseAddr) | TIM_ADV_DCR_DBL(conf->Length); in TIM_ADV_EnableDMABurst()

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