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Searched refs:CACHE_LINESIZE (Results 1 – 4 of 4) sorted by relevance

/bsp/k230/drivers/interdrv/sdio/
A Ddrv_sdhci.c38 #define CACHE_LINESIZE (64) macro
721 if (sz & (CACHE_LINESIZE - 1)) in kd_mmc_request()
722 pad = (sz + (CACHE_LINESIZE - 1)) & ~(CACHE_LINESIZE - 1); in kd_mmc_request()
723 if (sdhci_data.rxData && (((uint64_t)(sdhci_data.rxData) & (CACHE_LINESIZE - 1)) || pad)) in kd_mmc_request()
725 sdhci_data.rxData = rt_malloc_align(pad ? pad : sz, CACHE_LINESIZE); in kd_mmc_request()
726 } else if (((uint64_t)(sdhci_data.txData) & (CACHE_LINESIZE - 1)) || pad) in kd_mmc_request()
728 sdhci_data.txData = rt_malloc_align(pad ? pad : sz, CACHE_LINESIZE); in kd_mmc_request()
/bsp/nxp/imx/imxrt/libraries/drivers/
A Ddrv_sdio.c42 #define CACHE_LINESIZE (32) macro
245 if (((rt_uint32_t)data->buf & (CACHE_LINESIZE - 1)) || // align cache(32byte) in _mmc_request()
250 buf = rt_malloc_align(fsl_data.blockSize * fsl_data.blockCount, CACHE_LINESIZE); in _mmc_request()
/bsp/nxp/imx/imx6ull-smart/drivers/
A Ddrv_sdio.c33 #define CACHE_LINESIZE (32) macro
462 if (((rt_uint32_t)data->buf & (CACHE_LINESIZE - 1)) || // align cache(32byte) in _mmc_request()
467 buf = rt_malloc_align(fsl_data.blockSize * fsl_data.blockCount, CACHE_LINESIZE); in _mmc_request()
/bsp/hpmicro/libraries/drivers/
A Ddrv_sdio.c30 #define CACHE_LINESIZE HPM_L1C_CACHELINE_SIZE macro
37 #define SDXC_IS_CACHELINE_ALIGNED(n) ((uint32_t)(n) % (uint32_t)(CACHE_LINESIZE) == 0U)
470 raw_alloc_buf = (uint32_t *) rt_malloc(write_size + CACHE_LINESIZE - RT_ALIGN_SIZE); in hpm_sdmmc_request()
502 … raw_alloc_buf = (uint32_t *) rt_malloc(aligned_read_size + CACHE_LINESIZE - RT_ALIGN_SIZE); in hpm_sdmmc_request()

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