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Searched refs:CACHE_LINE_SIZE (Results 1 – 14 of 14) sorted by relevance

/bsp/allwinner_tina/libcpu/
A Dmmu.c141 ptr = buffer & ~(CACHE_LINE_SIZE - 1); in mmu_clean_invalidated_dcache()
146 ptr += CACHE_LINE_SIZE; in mmu_clean_invalidated_dcache()
154 ptr = buffer & ~(CACHE_LINE_SIZE - 1); in mmu_clean_dcache()
159 ptr += CACHE_LINE_SIZE; in mmu_clean_dcache()
167 ptr = buffer & ~(CACHE_LINE_SIZE - 1); in mmu_invalidate_dcache()
172 ptr += CACHE_LINE_SIZE; in mmu_invalidate_dcache()
331 ptr = buffer & ~(CACHE_LINE_SIZE - 1); in mmu_clean_invalidated_dcache()
337 ptr += CACHE_LINE_SIZE; in mmu_clean_invalidated_dcache()
346 ptr = buffer & ~(CACHE_LINE_SIZE - 1); in mmu_clean_dcache()
352 ptr += CACHE_LINE_SIZE; in mmu_clean_dcache()
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A Dmmu.h15 #define CACHE_LINE_SIZE 32 macro
/bsp/rockchip/common/drivers/
A Ddrv_heap.c84 #ifdef CACHE_LINE_SIZE in rt_dma_malloc_large()
85 align = CACHE_LINE_SIZE; in rt_dma_malloc_large()
186 #ifdef CACHE_LINE_SIZE in rt_dma_malloc_dtcm()
187 align = CACHE_LINE_SIZE; in rt_dma_malloc_dtcm()
277 #ifdef CACHE_LINE_SIZE in rt_dma_malloc_psram()
278 align = CACHE_LINE_SIZE; in rt_dma_malloc_psram()
/bsp/nuvoton/libraries/n9h30/rtt_port/
A Ddrv_crypto.c25 #define CACHE_LINE_SIZE 32 macro
257 if (((rt_uint32_t)in % CACHE_LINE_SIZE) != 0) in nu_aes_crypt()
259 in = rt_malloc_align(symmetric_info->length, CACHE_LINE_SIZE); in nu_aes_crypt()
270 if (((rt_uint32_t)out % CACHE_LINE_SIZE) != 0) in nu_aes_crypt()
272 out = rt_malloc_align(symmetric_info->length, CACHE_LINE_SIZE); in nu_aes_crypt()
449 if (((rt_uint32_t)in % CACHE_LINE_SIZE) != 0) in nu_des_crypt()
462 if (((rt_uint32_t)out % CACHE_LINE_SIZE) != 0) in nu_des_crypt()
663 if (((rt_uint32_t)nu_in % CACHE_LINE_SIZE) != 0) in nu_sha_update()
665 nu_in = rt_malloc_align(length, CACHE_LINE_SIZE); in nu_sha_update()
742 if (((rt_uint32_t)nu_out % CACHE_LINE_SIZE) != 0) in nu_sha_finish()
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A Ddrv_usbhost.c202 EP_INFO_T *psEPInfo = (EP_INFO_T *)rt_malloc_align(sizeof(EP_INFO_T), CACHE_LINE_SIZE); in GetFreePipe()
343 void *paddr = rt_malloc_align(512ul, CACHE_LINE_SIZE); in nu_open_pipe()
/bsp/rockchip/common/rk_hal/lib/hal/inc/
A Dhal_def.h66 #ifdef CACHE_LINE_SIZE
67 #define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), CACHE_LINE_SIZE)
79 #ifdef CACHE_LINE_SIZE
80 #define HAL_CACHELINE_ALIGNED __ALIGNED(CACHE_LINE_SIZE)
/bsp/k230/drivers/utest/
A Dtest_pdma.c37 #define CACHE_LINE_SIZE 64 macro
95 uint8_t *buf = rt_malloc_align(len, CACHE_LINE_SIZE); in test_pdma_tx()
172 uint8_t *buf = rt_malloc_align(64, CACHE_LINE_SIZE); in test_pdma_rx()
/bsp/rockchip/common/rk_hal/lib/hal/src/
A Dhal_cache.c242 offset = ((address & (CACHE_LINE_SIZE - 1)) + sizeByte - 1) >> CACHE_LINE_SHIFT; in HAL_ICACHE_InvalidateByRange()
585 offset = ((address & (CACHE_LINE_SIZE - 1)) + sizeByte - 1) >> CACHE_LINE_SHIFT; in HAL_DCACHE_InvalidateByRange()
629 offset = ((address & (CACHE_LINE_SIZE - 1)) + sizeByte - 1) >> CACHE_LINE_SHIFT; in HAL_DCACHE_CleanByRange()
673 offset = ((address & (CACHE_LINE_SIZE - 1)) + sizeByte - 1) >> CACHE_LINE_SHIFT; in HAL_DCACHE_CleanInvalidateByRange()
/bsp/rockchip/common/rk_hal/lib/CMSIS/Device/RK2108/Include/
A Dsoc.h171 #define CACHE_LINE_SIZE (0x1U << CACHE_LINE_SHIFT) macro
/bsp/nuvoton/libraries/ma35/rtt_port/
A Ddrv_pdma.c786 int CACHE_LINE_SIZE = nu_cpu_dcache_line_size(); in _nu_pdma_transfer() local
820 if ((u32FlushLen & (CACHE_LINE_SIZE - 1)) || in _nu_pdma_transfer()
821 (next->SA & (CACHE_LINE_SIZE - 1)) || in _nu_pdma_transfer()
822 (next->DA & (CACHE_LINE_SIZE - 1)) || in _nu_pdma_transfer()
823 ((rt_uint32_t)next & (CACHE_LINE_SIZE - 1))) in _nu_pdma_transfer()
/bsp/nuvoton/libraries/nuc980/rtt_port/
A Ddrv_pdma.c682 if ((u32FlushLen & (CACHE_LINE_SIZE - 1)) || in _nu_pdma_transfer()
683 (next->SA & (CACHE_LINE_SIZE - 1)) || in _nu_pdma_transfer()
684 (next->DA & (CACHE_LINE_SIZE - 1)) || in _nu_pdma_transfer()
685 ((rt_uint32_t)next & (CACHE_LINE_SIZE - 1))) in _nu_pdma_transfer()
A Ddrv_usbhost.c202 EP_INFO_T *psEPInfo = (EP_INFO_T *)rt_malloc_align(sizeof(EP_INFO_T), CACHE_LINE_SIZE); in GetFreePipe()
343 void *paddr = rt_malloc_align(512ul, CACHE_LINE_SIZE); in nu_open_pipe()
/bsp/dm365/drivers/
A Dmmcsd.c29 #define CACHE_LINE_SIZE 32 macro
787 addr = ((rt_uint32_t)data->buf & ~(CACHE_LINE_SIZE - 1)); in mmc_dm365_start_dma_transfer()
795 if (((rt_uint32_t)data->buf) & (CACHE_LINE_SIZE - 1)) in mmc_dm365_start_dma_transfer()
A Ddavinci_emac.c19 #define CACHE_LINE_SIZE 32 macro

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