Home
last modified time | relevance | path

Searched refs:CCMU_DBG (Results 1 – 6 of 6) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/
A Dcommon_ccmu.h38 #define CCMU_DBG(fmt,args...) printf("[CCMU:dbg..] %-*s:%d "fmt ,30, __func__, __LINE__, ##ar… macro
41 #define CCMU_DBG(fmt,args...) do{} while(0) macro
/bsp/allwinner/libraries/sunxi-hal/include/hal/
A Dhal_clk.h66 #define CCMU_DBG(fmt,args...) printf("[CCMU:dbg..] %-*s:%d "fmt ,30, __func__, __LINE__, ##ar… macro
69 #define CCMU_DBG(fmt,args...) do{} while(0) macro
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/
A Dclk.c663 CCMU_DBG("Clk-id %d init start.................\n", clk_init->clk); in sunxi_periph_bus_clk_init()
672 CCMU_DBG("set Parent-id %d \n", parent_clk); in sunxi_periph_bus_clk_init()
693 CCMU_DBG("get round rate %dHZ\n", round_rate); in sunxi_periph_bus_clk_init()
704 CCMU_DBG("set new rate %dHZ\n", round_rate); in sunxi_periph_bus_clk_init()
722CCMU_DBG("Clk-id %d cached rate %dHZ recalc new rate %dHZ, parent-id %d parent rate %dHZ \n", clk… in sunxi_periph_bus_clk_init()
724 CCMU_DBG("Clk-id %d init final .................\n", clk_init->clk); in sunxi_periph_bus_clk_init()
727 CCMU_DBG("ret %d \n", ret); in sunxi_periph_bus_clk_init()
A Dclk_periph.c58 CCMU_DBG("parent index %d \n", (*parent_index)); in sunxi_clk_periph_get_parent()
475 CCMU_DBG("parent rate %dHZ, target rate %dHZ, round rate %dHZ\n", prate, rate, round_rate); in sunxi_clk_periph_round_rate()
493 CCMU_DBG("parent rate %dHZ, set rate %dHZ\n", parent_rate, rate); in sunxi_clk_periph_set_rate()
542CCMU_DBG("divider->reg %d divider->mwidth %d divider->nshift %d \n", divider->reg, divider->mwidth… in sunxi_clk_periph_set_rate()
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/sun8iw18p1/
A Dclk_sun8iw18.c979 CCMU_DBG("clk %d current rate %d \n", factor->clk_core.clk, current_rate); in sunxi_factor_pll_cpu_init()
996 CCMU_DBG("clk %d recalc current rate %d \n", factor->clk_core.clk, current_rate); in sunxi_factor_pll_cpu_init()
1003 CCMU_DBG("clk init sucess! \n"); in sunxi_factor_pll_cpu_init()
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/sun8iw19p1/
A Dclk_sun8iw19.c1274 CCMU_DBG("clk %d current rate %d \n", factor->clk_core.clk, current_rate); in sunxi_factor_pll_cpu_init()
1291 CCMU_DBG("clk %d recalc current rate %d \n", factor->clk_core.clk, current_rate); in sunxi_factor_pll_cpu_init()
1298 CCMU_DBG("clk init sucess! \n"); in sunxi_factor_pll_cpu_init()

Completed in 25 milliseconds