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/bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/src/
A DHAL_dma.c108 DMAy_Channelx->CCR &= CCR_ENABLE_Reset; in DMA_DeInit()
110 DMAy_Channelx->CCR = 0; in DMA_DeInit()
176 tmpreg = DMAy_Channelx->CCR; in DMA_Init()
193 DMAy_Channelx->CCR = tmpreg; in DMA_Init()
255 DMAy_Channelx->CCR |= CCR_ENABLE_Set; in DMA_Cmd()
260 DMAy_Channelx->CCR &= CCR_ENABLE_Reset; in DMA_Cmd()
288 DMAy_Channelx->CCR |= DMA_IT; in DMA_ITConfig()
293 DMAy_Channelx->CCR &= ~DMA_IT; in DMA_ITConfig()
/bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/src/
A DHAL_dma.c111 DMAy_Channelx->CCR &= CCR_ENABLE_Reset; in DMA_DeInit()
113 DMAy_Channelx->CCR = 0; in DMA_DeInit()
186 tmpreg = DMAy_Channelx->CCR; in DMA_Init()
203 DMAy_Channelx->CCR = tmpreg; in DMA_Init()
265 DMAy_Channelx->CCR |= CCR_ENABLE_Set; in DMA_Cmd()
270 DMAy_Channelx->CCR &= CCR_ENABLE_Reset; in DMA_Cmd()
298 DMAy_Channelx->CCR |= DMA_IT; in DMA_ITConfig()
303 DMAy_Channelx->CCR &= ~DMA_IT; in DMA_ITConfig()
/bsp/tkm32F499/Libraries/Hal_lib/src/
A DHAL_dma_bak.c112 DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
114 DMAy_Channelx->CCR = 0;
180 tmpreg = DMAy_Channelx->CCR;
197 DMAy_Channelx->CCR = tmpreg;
259 DMAy_Channelx->CCR |= CCR_ENABLE_Set;
264 DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
292 DMAy_Channelx->CCR |= DMA_IT;
297 DMAy_Channelx->CCR &= ~DMA_IT;
A DHAL_dma.c114 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); in DMA_DeInit()
117 DMAy_Channelx->CCR = 0; in DMA_DeInit()
220 tmpreg = DMAy_Channelx->CCR; in DMA_Init()
238 DMAy_Channelx->CCR = tmpreg; in DMA_Init()
303 DMAy_Channelx->CCR |= DMA_CCR1_EN; in DMA_Cmd()
308 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); in DMA_Cmd()
335 DMAy_Channelx->CCR |= DMA_IT; in DMA_ITConfig()
340 DMAy_Channelx->CCR &= ~DMA_IT; in DMA_ITConfig()
/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/
A DHAL_dma.c111 DMAy_Channelx->CCR &= CCR_ENABLE_Reset; in DMA_DeInit()
113 DMAy_Channelx->CCR = 0; in DMA_DeInit()
186 tmpreg = DMAy_Channelx->CCR; in DMA_Init()
203 DMAy_Channelx->CCR = tmpreg; in DMA_Init()
265 DMAy_Channelx->CCR |= CCR_ENABLE_Set; in DMA_Cmd()
270 DMAy_Channelx->CCR &= CCR_ENABLE_Reset; in DMA_Cmd()
298 DMAy_Channelx->CCR |= DMA_IT; in DMA_ITConfig()
303 DMAy_Channelx->CCR &= ~DMA_IT; in DMA_ITConfig()
/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/
A Dhal_uart.c88 MODIFY_REG(uart->CCR, UART_CCR_CHAR, init_struct->WordLength); in UART_Init()
91 MODIFY_REG(uart->CCR, (UART_CCR_SPB0 | UART_CCR_SPB1), init_struct->StopBits); in UART_Init()
93 MODIFY_REG(uart->CCR, (UART_CCR_PEN | UART_CCR_PSEL), init_struct->Parity); in UART_Init()
261 MODIFY_REG(uart->CCR, UART_CCR_WAKE, mode); in UART_WakeUpConfig()
272 MODIFY_REG(uart->CCR, UART_CCR_RWU, state << UART_CCR_RWU_Pos); in UART_ReceiverWakeUpCmd()
305 MODIFY_REG(uart->CCR, UART_CCR_B8EN, state << UART_CCR_B8EN_Pos); in UART_Enable9bit()
316 MODIFY_REG(uart->CCR, UART_CCR_B8TXD, state << UART_CCR_B8TXD_Pos); in UART_Set9bitLevel()
327 MODIFY_REG(uart->CCR, UART_CCR_B8POL, polarity); in UART_Set9bitPolarity()
338 MODIFY_REG(uart->CCR, UART_CCR_B8TOG, state << UART_CCR_B8TOG_Pos); in UART_Set9bitAutomaticToggle()
396 SET_BIT(uart->CCR, UART_CCR_BRK); in UART_SendBreak()
A Dhal_dma.c50 channel->CCR &= ~DMA_CCR_EN; in DMA_DeInit()
51 channel->CCR = 0; in DMA_DeInit()
75 channel->CCR, in DMA_Init()
81 MODIFY_REG(channel->CCR, DMA_CCR_ARE, init_struct->DMA_Auto_reload); in DMA_Init()
119 MODIFY_REG(channel->CCR, DMA_CCR_EN, state << DMA_CCR_EN_Pos); in DMA_Cmd()
137 (state) ? (channel->CCR |= it) : (channel->CCR &= ~it); in DMA_ITConfig()
A Dhal_spi.c86 MODIFY_REG(spi->CCR, SPI_CCR_LSBFE, init_struct->SPI_FirstBit); in SPI_Init()
87 MODIFY_REG(spi->CCR, SPI_CCR_CPOL, init_struct->SPI_CPOL); in SPI_Init()
88 MODIFY_REG(spi->CCR, SPI_CCR_CPHA, init_struct->SPI_CPHA); in SPI_Init()
90 SET_BIT(spi->CCR, SPI_CCR_SPILEN); in SPI_Init()
447 (adjust_value) ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE); in SPI_SlaveAdjust()
528 adjust_value ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE); in exSPI_DataEdgeAdjust()
532 adjust_value ? SET_BIT(spi->CCR, SPI_CCR_TXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_TXEDGE); in exSPI_DataEdgeAdjust()
/bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/
A Dhal_dma.c43 DMAx->CH[channel].CCR = ccr; in DMA_InitChannel()
55 DMAx->CH[channel].CCR |= (interrupts & 0xEu); in DMA_EnableChannelInterrupts()
59 DMAx->CH[channel].CCR &= ~(interrupts & 0xEu); in DMA_EnableChannelInterrupts()
77 DMAx->CH[channel].CCR |= DMA_CCR_EN_MASK; in DMA_EnableChannel()
81 DMAx->CH[channel].CCR &= ~DMA_CCR_EN_MASK; in DMA_EnableChannel()
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/src/
A Dhk32f0xx_dma.c108 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); in DMA_DeInit()
111 DMAy_Channelx->CCR = 0; in DMA_DeInit()
177 tmpreg = DMAy_Channelx->CCR; in DMA_Init()
197 DMAy_Channelx->CCR = tmpreg; in DMA_Init()
263 DMAy_Channelx->CCR |= DMA_CCR_EN; in DMA_Cmd()
269 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); in DMA_Cmd()
417 DMAy_Channelx->CCR |= DMA_IT; in DMA_ITConfig()
422 DMAy_Channelx->CCR &= ~DMA_IT; in DMA_ITConfig()
/bsp/stm32/stm32l475-atk-pandora/board/ports/
A Ddrv_sdio_adapter.c46 DMA2_Channel4->CCR &= ~0x00000001; in SD_LowLevel_DMA_TxConfig()
53 DMA2_Channel4->CCR = DMA_MEMORY_TO_PERIPH | DMA_PINC_DISABLE | DMA_MINC_ENABLE | \ in SD_LowLevel_DMA_TxConfig()
59 DMA2_Channel4->CCR |= 0x00000001; in SD_LowLevel_DMA_TxConfig()
73 DMA2_Channel4->CCR &= ~0x00000001; in SD_LowLevel_DMA_RxConfig()
80 DMA2_Channel4->CCR = DMA_PERIPH_TO_MEMORY | DMA_PINC_DISABLE | DMA_MINC_ENABLE | \ in SD_LowLevel_DMA_RxConfig()
86 DMA2_Channel4->CCR |= 0x00000001; in SD_LowLevel_DMA_RxConfig()
/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/
A Dft32f0xx_dma.c62 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); in DMA_DeInit()
65 DMAy_Channelx->CCR = 0; in DMA_DeInit()
141 tmpreg = DMAy_Channelx->CCR; in DMA_Init()
161 DMAy_Channelx->CCR = tmpreg; in DMA_Init()
226 DMAy_Channelx->CCR |= DMA_CCR_EN; in DMA_Cmd()
231 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); in DMA_Cmd()
305 DMAy_Channelx->CCR |= DMA_IT; in DMA_ITConfig()
310 DMAy_Channelx->CCR &= ~DMA_IT; in DMA_ITConfig()
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_ll_dma.h531 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_IsEnabledChannel()
566 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_ConfigTransfer()
592 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_SetDataTransferDirection()
616 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetDataTransferDirection()
663 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetMode()
708 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetPeriphIncMode()
753 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetMemoryIncMode()
800 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetPeriphSize()
847 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetMemorySize()
896 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetChannelPriorityLevel()
[all …]
/bsp/airm2m/air32f103/libraries/AIR32F10xLib/src/
A Dair32f10x_dma.c90 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); in DMA_DeInit()
93 DMAy_Channelx->CCR = 0; in DMA_DeInit()
196 tmpreg = DMAy_Channelx->CCR; in DMA_Init()
214 DMAy_Channelx->CCR = tmpreg; in DMA_Init()
279 DMAy_Channelx->CCR |= DMA_CCR1_EN; in DMA_Cmd()
284 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); in DMA_Cmd()
311 DMAy_Channelx->CCR |= DMA_IT; in DMA_ITConfig()
316 DMAy_Channelx->CCR &= ~DMA_IT; in DMA_ITConfig()
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/
A Dht32f1xxxx_sci.c261 SCIx->CCR |= SCI_CLK_HARDWARE; in SCI_ClockModeConfig()
265 SCIx->CCR &= SCI_CLK_SOFTWARE; in SCI_ClockModeConfig()
285 SCIx->CCR |= SCI_CLK_HIGH; in SCI_SoftwareClockCmd()
289 SCIx->CCR &= SCI_CLK_LOW; in SCI_SoftwareClockCmd()
309 SCIx->CCR |= SCI_DIO_HIGH; in SCI_OutputDIO()
313 SCIx->CCR &= SCI_DIO_LOW; in SCI_OutputDIO()
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/
A Dht32f5xxxx_sci.c261 SCIx->CCR |= SCI_CLK_HARDWARE; in SCI_ClockModeConfig()
265 SCIx->CCR &= SCI_CLK_SOFTWARE; in SCI_ClockModeConfig()
285 SCIx->CCR |= SCI_CLK_HIGH; in SCI_SoftwareClockCmd()
289 SCIx->CCR &= SCI_CLK_LOW; in SCI_SoftwareClockCmd()
309 SCIx->CCR |= SCI_DIO_HIGH; in SCI_OutputDIO()
313 SCIx->CCR &= SCI_DIO_LOW; in SCI_OutputDIO()
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_mu.c116 uint32_t reg = base->CCR; in MU_BootCoreB()
120 base->CCR = reg; in MU_BootCoreB()
150 uint32_t ccr = base->CCR & ~(MU_CCR_HR_MASK | MU_CCR_RSTH_MASK | MU_CCR_BOOT_MASK); in MU_HardwareResetOtherCore()
164 base->CCR = ccr | MU_CCR_HR_MASK; in MU_HardwareResetOtherCore()
180 base->CCR = ccr; in MU_HardwareResetOtherCore()
/bsp/synwit/libraries/SWM341_CSL/CMSIS/CoreSupport/
A Dcachel1_armv7.h60 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
148 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
/bsp/airm2m/air32f103/libraries/CMSIS/Include/
A Dcachel1_armv7.h60 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
148 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/
A Dcachel1_armv7.h60 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
148 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
/bsp/tae32f5300/Libraries/CMSIS/Include/
A Dcachel1_armv7.h60 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
148 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
/bsp/renesas/ra8m1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h60 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
148 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h60 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
148 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/
A Dcachel1_armv7.h60 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
148 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
/bsp/renesas/ra8d1-vision-board/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h60 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
148 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()

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