| /bsp/hpmicro/libraries/hpm_sdk/drivers/src/ |
| A D | hpm_pllctl_drv.c | 32 if (!(ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK)) { in pllctl_set_pll_work_mode()
35 ptr->PLL[pll].CFG0 |= PLLCTL_PLL_CFG0_DSMPD_MASK; in pllctl_set_pll_work_mode()
39 if (ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK) { in pllctl_set_pll_work_mode()
42 ptr->PLL[pll].CFG0 &= ~PLLCTL_PLL_CFG0_DSMPD_MASK; in pllctl_set_pll_work_mode()
61 if (ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK) { in pllctl_set_refdiv()
74 ptr->PLL[pll].CFG0 = (ptr->PLL[pll].CFG0 & ~PLLCTL_PLL_CFG0_REFDIV_MASK) in pllctl_set_refdiv()
94 refdiv = PLLCTL_PLL_CFG0_REFDIV_GET(ptr->PLL[pll].CFG0); in pllctl_init_int_pll_with_freq()
132 ptr->PLL[pll].CFG0 |= PLLCTL_PLL_CFG0_DSMPD_MASK; in pllctl_init_int_pll_with_freq()
138 ptr->PLL[pll].CFG0 = (ptr->PLL[pll].CFG0 & ~PLLCTL_PLL_CFG0_REFDIV_MASK) in pllctl_init_int_pll_with_freq()
207 ptr->PLL[pll].CFG0 = (ptr->PLL[pll].CFG0 in pllctl_init_frac_pll_with_freq()
[all …]
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| A D | hpm_pwmv2_drv.c | 32 pwm_x->PWM[i].CFG0 = 0; in pwmv2_deinit()
37 pwm_x->CAL[i].CFG0 = 0; in pwmv2_deinit()
65 …pwm_x->PWM[index].CFG0 = (pwm_x->PWM[index].CFG0 & ~(PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK | PWMV2_P… in pwmv2_config_async_fault_source()
73 pwm_x->PWM[index].CFG0 = PWMV2_PWM_CFG0_TRIG_SEL4_SET(config->enable_four_cmp) | in pwmv2_config_pwm()
123 pwm_x->CAL[cal_index].CFG0 = PWMV2_CAL_CFG0_CAL_LU_PARAM_SET(cal->up_limit_param) | in pwmv2_setup_cmp_calculate()
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| A D | hpm_dac_drv.c | 39 ptr->CFG0 = ptr->CFG0_BAK; in dac_init()
118 ptr->CFG0 = ptr->CFG0_BAK; in dac_set_buffer_config()
159 ptr->CFG0 = ptr->CFG0_BAK; in dac_set_buffer_config()
175 ptr->CFG0 = ptr->CFG0_BAK; in dac_set_direct_config()
203 ptr->CFG0 = ptr->CFG0_BAK; in dac_set_step_sw_trigger()
217 ptr->CFG0 = ptr->CFG0_BAK; in dac_set_buffer_sw_trigger()
234 ptr->CFG0 = ptr->CFG0_BAK; in dac_set_hw_trigger_enable()
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| A D | hpm_gwc_drv.c | 39 ptr->CHANNEL[ch_index].CFG0 = GWC_CHANNEL_CFG0_START_ROW_SET(cfg->start_row) | in gwc_ch_init()
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| A D | hpm_ppi_drv.c | 34 ppi->CS[index].CFG0 = tmp; in ppi_config_cs_pin()
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| A D | hpm_opamp_drv.c | 115 opamp->CFG[preset_chn].CFG0 = 0; in opamp_set_preset_cfg()
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| /bsp/hpmicro/libraries/hpm_sdk/drivers/inc/ |
| A D | hpm_pwmv2_drv.h | 395 …pwm_x->PWM[chn].CFG0 = (pwm_x->PWM[chn].CFG0 & ~PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK) | PWMV2_PWM_C… in pwmv2_fault_signal_select_from_pad()
407 …pwm_x->PWM[chn].CFG0 = (pwm_x->PWM[chn].CFG0 & ~PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK) | PWMV2_PWM_C… in pwmv2_fault_signal_polarity()
486 …pwm_x->PWM[chn].CFG0 = (pwm_x->PWM[chn].CFG0 & ~PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK) | PWMV2_PWM_CF… in pwmv2_enable_invert_by_shadow()
1323 …pwm_x->CNT[counter].CFG0 = (pwm_x->CNT[counter].CFG0 & ~(PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK)) | PWMV… in pwmv2_reload_select_compare_point0_index()
1335 …pwm_x->CNT[counter].CFG0 = (pwm_x->CNT[counter].CFG0 & ~(PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK)) | PWMV… in pwmv2_reload_select_compare_point1_index()
1347 …pwm_x->CNT[counter].CFG0 = (pwm_x->CNT[counter].CFG0 & ~(PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK)) | PWMV… in pwmv2_reload_select_input_trigger()
1371 …pwm_x->CNT[counter].CFG0 = (pwm_x->CNT[counter].CFG0 & ~PWMV2_CNT_CFG0_CNT_D_PARAM_MASK) | PWMV2_C… in pwmv2_counter_set_dac_data_parameter()
1691 …pwm_x->CAL[cal_index].CFG0 = (pwm_x->CAL[cal_index].CFG0 & ~PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK) | PW… in pwmv2_calculate_set_up_limit_parameter()
1703 …pwm_x->CAL[cal_index].CFG0 = (pwm_x->CAL[cal_index].CFG0 & ~PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK) | PW… in pwmv2_calculate_set_low_limit_parameter()
1715 …pwm_x->CAL[cal_index].CFG0 = (pwm_x->CAL[cal_index].CFG0 & ~PWMV2_CAL_CFG0_CAL_T_PARAM_MASK) | PWM… in pwmv2_calculate_set_period_parameter()
[all …]
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| A D | hpm_opamp_drv.h | 235 …opamp->CFG[preset_chn].CFG0 = (opamp->CFG[preset_chn].CFG0 & (~OPAMP_CFG_CFG0_MILLER_SEL_MASK)) | … in opamp_preset_miller_cap_select()
256 opamp->CFG[preset_chn].CFG0 &= ~OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK; in opamp_preset_phase_margin_cap_enable()
277 opamp->CFG[preset_chn].CFG0 |= OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK; in opamp_preset_phase_margin_cap_disable()
300 …opamp->CFG[preset_chn].CFG0 = (opamp->CFG[preset_chn].CFG0 & (~OPAMP_CFG_CFG0_VIM_SEL_MASK)) | OPA… in opamp_preset_inn_pad_select()
390 …opamp->CFG[preset_chn].CFG0 = (opamp->CFG[preset_chn].CFG0 & (~OPAMP_CFG_CFG0_VIP_SEL_MASK)) | OPA… in opamp_preset_inp_pad_select()
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| A D | hpm_pllctl_drv.h | 90 ptr->PLL[pll].CFG0 |= (PLLCTL_PLL_CFG0_SS_RSTPTR_MASK in pllctl_pll_ss_disable()
92 ptr->PLL[pll].CFG0 |= PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK; in pllctl_pll_ss_disable()
173 ptr->PLL[pll].CFG0 &= ~(PLLCTL_PLL_CFG0_SS_RSTPTR_MASK in pllctl_pll_ss_enable()
175 ptr->PLL[pll].CFG0 &= ~PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK; in pllctl_pll_ss_enable()
176 ptr->PLL[pll].CFG0 = (ptr->PLL[pll].CFG0 in pllctl_pll_ss_enable()
203 …ptr->PLL[pll].CFG0 = ((ptr->PLL[pll].CFG0 & ~(PLLCTL_PLL_CFG0_POSTDIV1_MASK))) | PLLCTL_PLL_CFG0_P… in pllctl_set_postdiv1()
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| A D | hpm_gwc_drv.h | 164 ptr->CHANNEL[ch_index].CFG0 |= GWC_CHANNEL_CFG0_ENABLE_MASK; in gwc_ch_enable()
176 ptr->CHANNEL[ch_index].CFG0 &= ~GWC_CHANNEL_CFG0_ENABLE_MASK; in gwc_ch_disable()
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| /bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/ |
| A D | hpm_gwc_regs.h | 18 __RW uint32_t CFG0; /* 0x10: config reg 0 */ member
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| /bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/ |
| A D | hpm_opamp_regs.h | 18 __RW uint32_t CFG0; /* 0x10: */ member
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| A D | hpm_dac_regs.h | 13 __W uint32_t CFG0; /* 0x0: */ member
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| /bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/ |
| A D | hpm_pllctl_regs.h | 16 __RW uint32_t CFG0; /* 0x80: PLLx config0 */ member
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| /bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/ |
| A D | hpm_pwmv2_regs.h | 20 __RW uint32_t CFG0; /* 0x100: */ member
62 __RW uint32_t CFG0; /* 0x500: */ member
70 __RW uint32_t CFG0; /* 0x600: */ member
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| A D | hpm_ppi_regs.h | 23 __RW uint32_t CFG0; /* 0x40: cfg0 */ member
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| /bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/ |
| A D | hpm_dac_regs.h | 13 __W uint32_t CFG0; /* 0x0: */ member
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| /bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/ |
| A D | hpm_dac_regs.h | 13 __W uint32_t CFG0; /* 0x0: */ member
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| /bsp/nxp/imx/imx6ull-smart/drivers/ |
| A D | drv_eth.c | 287 uid[0] = ocotp_base->CFG0; in rt_imx6ul_eth_control()
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| /bsp/synwit/libraries/SWM320_CSL/CMSIS/DeviceSupport/ |
| A D | SWM320.h | 2711 __IO uint32_t CFG0; member
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| /bsp/synwit/libraries/SWM341_CSL/CMSIS/DeviceSupport/ |
| A D | SWM341.h | 2870 __IO uint32_t CFG0; member
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| /bsp/apm32/libraries/APM32S10x_Library/Device/Geehy/APM32S10x/Include/ |
| A D | apm32s10x.h | 514 __IOM uint32_t CFG0 : 2; member
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| /bsp/apm32/libraries/APM32E10x_Library/Device/Geehy/APM32E10x/Include/ |
| A D | apm32e10x.h | 542 __IOM uint32_t CFG0 : 2; member
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| /bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/ |
| A D | apm32f10x.h | 717 __IOM uint32_t CFG0 : 2; member
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| /bsp/CME_M7/StdPeriph_Driver/inc/ |
| A D | cmem7.h | 993 …__IO uint32_t CFG0; /*!< config Register … member
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