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Searched refs:CFG0_PLLMF (Results 1 – 1 of 1) sorted by relevance

/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/
A Dgd32vf103_rcu.h480 #define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) macro
481 #define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock m…
482 #define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock m…
483 #define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock m…
484 #define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock m…
485 #define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock m…
486 #define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock m…
487 #define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock m…
488 #define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock m…
489 #define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock m…
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