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Searched refs:CFGR (Results 1 – 25 of 144) sorted by relevance

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/bsp/mm32l3xx/Libraries/MM32L3xx/Source/
A Dsystem_MM32L3xx.c191 RCC->CFGR &= (uint32_t)0xF8FF000C; in SystemInit()
200 RCC->CFGR &= (uint32_t)0xFF80FFFF; in SystemInit()
379 RCC->CFGR &= (uint32_t)0xFFFCFFFF; in SetSysClockTo24()
467 RCC->CFGR &= (uint32_t)0xFFFCFFFF; in SetSysClockTo36()
553 RCC->CFGR &= (uint32_t)0xFFFCFFFF; in SetSysClockTo48()
869 RCC->CFGR&=~RCC_CFGR_SW; in SetSysClockTo48_HSI()
873 temp=RCC->CFGR>>2; in SetSysClockTo48_HSI()
896 RCC->CFGR&=~RCC_CFGR_SW; in SetSysClockTo72_HSI()
900 temp=RCC->CFGR>>2; in SetSysClockTo72_HSI()
923 RCC->CFGR&=~RCC_CFGR_SW; in SetSysClockTo96_HSI()
[all …]
/bsp/mm32f103x/Libraries/MM32F103/Source/
A Dsystem_MM32F103.c191 RCC->CFGR &= (uint32_t)0xF8FF000C; in SystemInit()
200 RCC->CFGR &= (uint32_t)0xFF80FFFF; in SystemInit()
384 RCC->CFGR &= (uint32_t)0xFFFCFFFF; in SetSysClockTo24()
475 RCC->CFGR &= (uint32_t)0xFFFCFFFF; in SetSysClockTo36()
564 RCC->CFGR &= (uint32_t)0xFFFCFFFF; in SetSysClockTo48()
890 RCC->CFGR &= ~RCC_CFGR_SW; in SetSysClockTo48_HSI()
894 temp = RCC->CFGR >> 2; in SetSysClockTo48_HSI()
917 RCC->CFGR &= ~RCC_CFGR_SW; in SetSysClockTo72_HSI()
921 temp = RCC->CFGR >> 2; in SetSysClockTo72_HSI()
944 RCC->CFGR &= ~RCC_CFGR_SW; in SetSysClockTo96_HSI()
[all …]
/bsp/mm32l07x/Libraries/MM32L0xx/Source/
A Dsystem_MM32L0xx.c181 RCC->CFGR &= (uint32_t)0xF8FFC00C; in SystemInit()
190 RCC->CFGR &= (uint32_t)0xFF3CFFFF; in SystemInit()
360 RCC->CFGR &= (uint32_t)0xFFFCFFFF; in SetSysClockTo24()
447 RCC->CFGR &= (uint32_t)0xFFFCFFFF; in SetSysClockTo36()
533 RCC->CFGR &= (uint32_t)0xFFFCFFFF; in SetSysClockTo48()
582 RCC->CFGR&=~RCC_CFGR_SW; in SetSysClockTo24_HSI()
586 temp=RCC->CFGR>>2; in SetSysClockTo24_HSI()
611 RCC->CFGR&=~RCC_CFGR_SW; in SetSysClockTo36_HSI()
615 temp=RCC->CFGR>>2; in SetSysClockTo36_HSI()
640 RCC->CFGR&=~RCC_CFGR_SW; in SetSysClockTo48_HSI()
[all …]
/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/
A Dsystem_ft32f0xx.c133 RCC->CFGR &= (uint32_t)0xF8FFB80C; in SystemInit()
142 RCC->CFGR &= (uint32_t)0xFFC0FFFF; in SystemInit()
200 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
212 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; in SystemCoreClockUpdate()
315 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; in SetSysClockToHSE()
384 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; in SetSysClockTo24()
453 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; in SetSysClockTo36()
522 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; in SetSysClockTo48()
591 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; in SetSysClockTo56()
660 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; in SetSysClockTo72()
[all …]
/bsp/airm2m/air32f103/libraries/AIR32F10xLib/src/
A Dsystem_air32f10x.c220 RCC->CFGR &= (uint32_t)0xF8FF0000; in SystemInit()
222 RCC->CFGR &= (uint32_t)0xF0FF0000; in SystemInit()
232 RCC->CFGR &= (uint32_t)0xFF80FFFF; in SystemInit()
319 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
332 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; in SystemCoreClockUpdate()
559 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; in SetSysClockToHSE()
663 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; in SetSysClockTo24()
764 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; in SetSysClockTo36()
864 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; in SetSysClockTo48()
966 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; in SetSysClockTo56()
[all …]
A Dair32f10x_rcc.c299 tmpreg = RCC->CFGR; in RCC_PLLConfig()
305 RCC->CFGR = tmpreg; in RCC_PLLConfig()
336 tmpreg = RCC->CFGR; in RCC_SYSCLKConfig()
342 RCC->CFGR = tmpreg; in RCC_SYSCLKConfig()
380 tmpreg = RCC->CFGR; in RCC_HCLKConfig()
386 RCC->CFGR = tmpreg; in RCC_HCLKConfig()
406 tmpreg = RCC->CFGR; in RCC_PCLK1Config()
412 RCC->CFGR = tmpreg; in RCC_PCLK1Config()
432 tmpreg = RCC->CFGR; in RCC_PCLK2Config()
438 RCC->CFGR = tmpreg; in RCC_PCLK2Config()
[all …]
/bsp/mm32f327x/Libraries/MM32F327x/Source/
A Dsystem_mm32f327x.c174 RCC->CFGR &= (u32)0xF8FFC00C; in SystemInit()
183 RCC->CFGR &= (u32)0xFF3CFFFF; in SystemInit()
673 RCC->CFGR = RCC_CFGR_PPRE1_2; in SetSysClockTo24_HSI()
687 RCC->CFGR &= ~RCC_CFGR_SW; in SetSysClockTo24_HSI()
689 RCC->CFGR |= RCC_CFGR_SW_PLL; in SetSysClockTo24_HSI()
692 temp = RCC->CFGR >> 2; in SetSysClockTo24_HSI()
706 RCC->CFGR = RCC_CFGR_PPRE1_2; in SetSysClockTo36_HSI()
719 RCC->CFGR &= ~ RCC_CFGR_SW; in SetSysClockTo36_HSI()
724 temp = RCC->CFGR >> 2; in SetSysClockTo36_HSI()
756 RCC->CFGR &= ~RCC_CFGR_SW; in SetSysClockTo48_HSI()
[all …]
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Source/
A Dsystem_hk32f0xx.c145 RCC->CFGR &= (uint32_t)0xF8FFB80C; in SystemInit()
154 RCC->CFGR &= (uint32_t)0xFFC0FFFF; in SystemInit()
212 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
224 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
225 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; in SystemCoreClockUpdate()
246 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; in SystemCoreClockUpdate()
295 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; in SetSysClock()
298 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; in SetSysClock()
313 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); in SetSysClock()
314 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; in SetSysClock()
[all …]
/bsp/mm32/mm32f3270-100ask-pitaya/board/
A Dboard.c50 RCC->CFGR |= (0<<4); // AHB不分频 in SystemClock_Config()
51 RCC->CFGR |= (4<<8); // APB1 2分频 in SystemClock_Config()
52 RCC->CFGR |= (4<<11); // APB2 2分频 in SystemClock_Config()
53 RCC->CFGR |= (2<<22); // PLL输出时钟3分频后输出给USB：120MHz/3=40MHz in SystemClock_Config()
54 RCC->CFGR |= (7<<24); // PLL输出时钟2分频后输出到MCO in SystemClock_Config()
55 RCC->CFGR |= (2<<0); // 选择PLL输出用作系统时钟 in SystemClock_Config()
56 while(0 == (RCC->CFGR & (2<<2))); // 等待PLL输出用作系统时钟稳定 in SystemClock_Config()
69 tmpreg = RCC->CFGR; in update_systemclock()
120 uint32_t tmpreg = RCC->CFGR; in update_ahb_clock()
133 uint32_t tmpreg = RCC->CFGR; in update_apb1_clock()
[all …]
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/
A Dht32f5xxxx_usbd.c109 pDriver->ept[USBD_EPT0].CFGR.word = _EP0_CFG; in USBD_PreInit()
411 USBEPn->CFGR = pDrv->ept[USBD_EPTn].CFGR.word; in USBD_EPTInit()
486 USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); in USBD_EPTGetHalt() local
487 if (CFGR->EPDIR == EPDIR_IN) in USBD_EPTGetHalt()
524 USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); in USBD_EPTSetHalt() local
525 if (CFGR->EPDIR == EPDIR_IN) in USBD_EPTSetHalt()
555 USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); in USBD_EPTClearHalt() local
556 if (CFGR->EPDIR == EPDIR_IN) in USBD_EPTClearHalt()
580 USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); in USBD_EPTWaitSTALLSent() local
604 USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); in USBD_EPTClearDTG() local
[all …]
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/
A Dht32f1xxxx_usbd.c109 pDriver->ept[USBD_EPT0].CFGR.word = _EP0_CFG; in USBD_PreInit()
400 USBEPn->CFGR = pDrv->ept[USBD_EPTn].CFGR.word; in USBD_EPTInit()
475 USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); in USBD_EPTGetHalt() local
476 if (CFGR->EPDIR == EPDIR_IN) in USBD_EPTGetHalt()
513 USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); in USBD_EPTSetHalt() local
514 if (CFGR->EPDIR == EPDIR_IN) in USBD_EPTSetHalt()
544 USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); in USBD_EPTClearHalt() local
545 if (CFGR->EPDIR == EPDIR_IN) in USBD_EPTClearHalt()
569 USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); in USBD_EPTWaitSTALLSent() local
593 USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); in USBD_EPTClearDTG() local
[all …]
/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/
A Dft32f0xx_crs.c123 CRS->CFGR &= ~CRS_CFGR_RELOAD; in CRS_FrequencyErrorCounterReload()
126 CRS->CFGR |= (uint32_t)CRS_ReloadValue; in CRS_FrequencyErrorCounterReload()
140 CRS->CFGR &= ~CRS_CFGR_FELIM; in CRS_FrequencyErrorLimitConfig()
143 CRS->CFGR |= (uint32_t)(CRS_ErrorLimitValue <<16); in CRS_FrequencyErrorLimitConfig()
167 CRS->CFGR &= ~CRS_CFGR_SYNCDIV; in CRS_SynchronizationPrescalerConfig()
170 CRS->CFGR |= CRS_Prescaler; in CRS_SynchronizationPrescalerConfig()
189 CRS->CFGR &= ~CRS_CFGR_SYNCSRC; in CRS_SynchronizationSourceConfig()
192 CRS->CFGR |= CRS_Source; in CRS_SynchronizationSourceConfig()
210 CRS->CFGR &= ~CRS_CFGR_SYNCPOL; in CRS_SynchronizationPolarityConfig()
213 CRS->CFGR |= CRS_Polarity; in CRS_SynchronizationPolarityConfig()
[all …]
A Dft32f0xx_rcc.c59 RCC->CFGR &= (uint32_t)0x08FFB80C; in RCC_DeInit()
68 RCC->CFGR &= (uint32_t)0xFFC0FFFF; in RCC_DeInit()
539 tmpreg = RCC->CFGR; in RCC_MCOConfig()
545 RCC->CFGR = tmpreg; in RCC_MCOConfig()
578 tmpreg = RCC->CFGR; in RCC_SYSCLKConfig()
587 RCC->CFGR = tmpreg; in RCC_SYSCLKConfig()
628 tmpreg = RCC->CFGR; in RCC_HCLKConfig()
637 RCC->CFGR = tmpreg; in RCC_HCLKConfig()
659 tmpreg = RCC->CFGR; in RCC_PCLKConfig()
668 RCC->CFGR = tmpreg; in RCC_PCLKConfig()
[all …]
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/
A Dfm33lc0xx_fl_adc.h802 SET_BIT(ADCx->CFGR, ADC_CFGR_DMAEN_Msk); in FL_ADC_EnableDMAReq()
813 CLEAR_BIT(ADCx->CFGR, ADC_CFGR_DMAEN_Msk); in FL_ADC_DisableDMAReq()
930 SET_BIT(ADCx->CFGR, ADC_CFGR_OVRM_Msk); in FL_ADC_EnableOverrunMode()
941 CLEAR_BIT(ADCx->CFGR, ADC_CFGR_OVRM_Msk); in FL_ADC_DisableOverrunMode()
990 SET_BIT(ADCx->CFGR, ADC_CFGR_WAIT_Msk); in FL_ADC_EnableWaitMode()
1001 CLEAR_BIT(ADCx->CFGR, ADC_CFGR_WAIT_Msk); in FL_ADC_DisableWaitMode()
1081 SET_BIT(ADCx->CFGR, ADC_CFGR_IOTRFEN_Msk); in FL_ADC_EnableTriggerFilter()
1114 SET_BIT(ADCx->CFGR, ADC_CFGR_OVSEN_Msk); in FL_ADC_EnableOverSampling()
1125 CLEAR_BIT(ADCx->CFGR, ADC_CFGR_OVSEN_Msk); in FL_ADC_DisableOverSampling()
1227 SET_BIT(ADCx->CFGR, ADC_CFGR_AWDEN_Msk); in FL_ADC_EnableAnalogWDG()
[all …]
A Dfm33lc0xx_fl_svd.h218 MODIFY_REG(SVDx->CFGR, SVD_CFGR_ADSVD_SEL_Msk, level); in FL_SVD_SetADCThreshold()
237 return (uint32_t)(READ_BIT(SVDx->CFGR, SVD_CFGR_ADSVD_SEL_Msk)); in FL_SVD_GetADCThreshold()
248 SET_BIT(SVDx->CFGR, SVD_CFGR_ADSVD_EN_Msk); in FL_SVD_EnableADCMonitor()
270 CLEAR_BIT(SVDx->CFGR, SVD_CFGR_ADSVD_EN_Msk); in FL_SVD_DisableADCMonitor()
298 MODIFY_REG(SVDx->CFGR, SVD_CFGR_LVL_Msk, level); in FL_SVD_SetWarningThreshold()
325 return (uint32_t)(READ_BIT(SVDx->CFGR, SVD_CFGR_LVL_Msk)); in FL_SVD_GetWarningThreshold()
336 SET_BIT(SVDx->CFGR, SVD_CFGR_DFEN_Msk); in FL_SVD_EnableDigitalFilter()
347 return (uint32_t)(READ_BIT(SVDx->CFGR, SVD_CFGR_DFEN_Msk) == SVD_CFGR_DFEN_Msk); in FL_SVD_IsEnabledDigitalFilter()
358 CLEAR_BIT(SVDx->CFGR, SVD_CFGR_DFEN_Msk); in FL_SVD_DisableDigitalFilter()
372 MODIFY_REG(SVDx->CFGR, SVD_CFGR_MOD_Msk, mode); in FL_SVD_SetWorkMode()
[all …]
/bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/src/
A DHAL_rcc.c382 tmpreg = RCC->CFGR; in RCC_PLLConfig()
388 RCC->CFGR = tmpreg; in RCC_PLLConfig()
491 tmpreg = RCC->CFGR; in RCC_SYSCLKConfig()
497 RCC->CFGR = tmpreg; in RCC_SYSCLKConfig()
536 tmpreg = RCC->CFGR; in RCC_HCLKConfig()
542 RCC->CFGR = tmpreg; in RCC_HCLKConfig()
562 tmpreg = RCC->CFGR; in RCC_PCLK1Config()
568 RCC->CFGR = tmpreg; in RCC_PCLK1Config()
588 tmpreg = RCC->CFGR; in RCC_PCLK2Config()
594 RCC->CFGR = tmpreg; in RCC_PCLK2Config()
[all …]
A DHAL_syscfg.c82 SYSCFG->CFGR &= SYSCFG_CFGR_MEM_MODE; in SYSCFG_DeInit()
108 tmpctrl = SYSCFG->CFGR; in SYSCFG_MemoryRemapConfig()
117 SYSCFG->CFGR = tmpctrl; in SYSCFG_MemoryRemapConfig()
149 SYSCFG->CFGR |= (uint32_t)SYSCFG_DMARemap; in SYSCFG_DMAChannelRemapConfig()
154 SYSCFG->CFGR &= (uint32_t)(~SYSCFG_DMARemap); in SYSCFG_DMAChannelRemapConfig()
/bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/src/
A DHAL_rcc.c363 tmpreg = RCC->CFGR; in RCC_PLLConfig()
369 RCC->CFGR = tmpreg; in RCC_PLLConfig()
470 tmpreg = RCC->CFGR; in RCC_SYSCLKConfig()
476 RCC->CFGR = tmpreg; in RCC_SYSCLKConfig()
514 tmpreg = RCC->CFGR; in RCC_HCLKConfig()
520 RCC->CFGR = tmpreg; in RCC_HCLKConfig()
540 tmpreg = RCC->CFGR; in RCC_PCLK1Config()
546 RCC->CFGR = tmpreg; in RCC_PCLK1Config()
566 tmpreg = RCC->CFGR; in RCC_PCLK2Config()
572 RCC->CFGR = tmpreg; in RCC_PCLK2Config()
[all …]
/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/
A DHAL_rcc.c364 tmpreg = RCC->CFGR; in RCC_PLLConfig()
370 RCC->CFGR = tmpreg; in RCC_PLLConfig()
471 tmpreg = RCC->CFGR; in RCC_SYSCLKConfig()
477 RCC->CFGR = tmpreg; in RCC_SYSCLKConfig()
515 tmpreg = RCC->CFGR; in RCC_HCLKConfig()
521 RCC->CFGR = tmpreg; in RCC_HCLKConfig()
541 tmpreg = RCC->CFGR; in RCC_PCLK1Config()
547 RCC->CFGR = tmpreg; in RCC_PCLK1Config()
567 tmpreg = RCC->CFGR; in RCC_PCLK2Config()
573 RCC->CFGR = tmpreg; in RCC_PCLK2Config()
[all …]
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/src/
A Dhk32f0xx_rcc.c126 RCC->CFGR &= (uint32_t)0xF8FFB80C; in RCC_DeInit()
129 RCC->CFGR &= (uint32_t)0x08FFB80C; in RCC_DeInit()
625 tmpreg = RCC->CFGR; in RCC_MCOConfig()
631 RCC->CFGR = tmpreg; in RCC_MCOConfig()
738 tmpreg = RCC->CFGR; in RCC_SYSCLKConfig()
747 RCC->CFGR = tmpreg; in RCC_SYSCLKConfig()
787 tmpreg = RCC->CFGR; in RCC_HCLKConfig()
796 RCC->CFGR = tmpreg; in RCC_HCLKConfig()
818 tmpreg = RCC->CFGR; in RCC_PCLKConfig()
827 RCC->CFGR = tmpreg; in RCC_PCLKConfig()
[all …]
/bsp/tkm32F499/Libraries/Hal_lib/src/
A DHAL_rcc.c395 tmpreg = RCC->CFGR; in RCC_PLLConfig()
401 RCC->CFGR = tmpreg; in RCC_PLLConfig()
577 tmpreg = RCC->CFGR; in RCC_SYSCLKConfig()
583 RCC->CFGR = tmpreg; in RCC_SYSCLKConfig()
640 tmpreg = RCC->CFGR; in RCC_HCLKConfig()
646 RCC->CFGR = tmpreg; in RCC_HCLKConfig()
666 tmpreg = RCC->CFGR; in RCC_PCLK1Config()
672 RCC->CFGR = tmpreg; in RCC_PCLK1Config()
692 tmpreg = RCC->CFGR; in RCC_PCLK2Config()
698 RCC->CFGR = tmpreg; in RCC_PCLK2Config()
[all …]
A DHAL_syscfg.c82 SYSCFG->CFGR &= SYSCFG_CFGR_MEM_MODE; in SYSCFG_DeInit()
108 tmpctrl = SYSCFG->CFGR; in SYSCFG_MemoryRemapConfig()
117 SYSCFG->CFGR = tmpctrl; in SYSCFG_MemoryRemapConfig()
149 SYSCFG->CFGR |= (uint32_t)SYSCFG_DMARemap; in SYSCFG_DMAChannelRemapConfig()
154 SYSCFG->CFGR &= (uint32_t)(~SYSCFG_DMARemap); in SYSCFG_DMAChannelRemapConfig()
/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/
A Dhal_wwdg.c60 WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WDGTB) | prescaler; in WWDG_SetPrescaler()
72 WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WINDOW) | (window_value & WWDG_CFGR_WINDOW); in WWDG_SetWindowValue()
84 WWDG->CFGR |= WWDG_CFGR_EWI; in WWDG_EnableIT()
/bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/StdPeriph_Driver/src/
A Dch32f20x_wwdg.c44 tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; in WWDG_SetPrescaler()
46 WWDG->CFGR = tmpreg; in WWDG_SetPrescaler()
60 tmpreg = WWDG->CFGR & CFGR_W_Mask; in WWDG_SetWindowValue()
64 WWDG->CFGR = tmpreg; in WWDG_SetWindowValue()
75 WWDG->CFGR |= (1<<9); in WWDG_EnableIT()
/bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/
A Dch32v10x_wwdg.c50 tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; in WWDG_SetPrescaler()
52 WWDG->CFGR = tmpreg; in WWDG_SetPrescaler()
69 tmpreg = WWDG->CFGR & CFGR_W_Mask; in WWDG_SetWindowValue()
73 WWDG->CFGR = tmpreg; in WWDG_SetWindowValue()
85 WWDG->CFGR |= (1 << 9); in WWDG_EnableIT()

Completed in 3584 milliseconds

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