| /bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/StdPeriph_Driver/src/ |
| A D | ch32f20x_rcc.c | 959 tmpreg = RCC->CFGR2; in RCC_PREDIV1Config()
962 RCC->CFGR2 = tmpreg; in RCC_PREDIV1Config()
976 tmpreg = RCC->CFGR2; in RCC_PREDIV2Config()
979 RCC->CFGR2 = tmpreg; in RCC_PREDIV2Config()
993 tmpreg = RCC->CFGR2; in RCC_PLL2Config()
996 RCC->CFGR2 = tmpreg; in RCC_PLL2Config()
1027 tmpreg = RCC->CFGR2; in RCC_PLL3Config()
1030 RCC->CFGR2 = tmpreg; in RCC_PLL3Config()
1171 RCC->CFGR2 |= ((uint32_t)1<<22); in RCC_ETH1G_125Mcmd()
1196 RCC->CFGR2 |= RCC_USBHS<<24; in RCC_USBHSConfig()
[all …]
|
| /bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/ |
| A D | hal_syscfg.c | 58 SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_I2C1MODESEL_MASK ) in SYSCFG_SetI2C0PortMode()
64 SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_I2C2MODESEL_MASK ) in SYSCFG_SetI2C1PortMode()
70 SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_MIIRMIISEL_MASK ) in SYSCFG_SetENETPortMode()
76 SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_MACSPDSEL_MASK ) in SYSCFG_SetENETSpeedMode()
|
| /bsp/airm2m/air32f103/libraries/AIR32F10xLib/src/ |
| A D | system_air32f10x.c | 242 RCC->CFGR2 = 0x00000000; in SystemInit()
248 RCC->CFGR2 = 0x00000000; in SystemInit()
346 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; in SystemCoreClockUpdate()
382 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; in SystemCoreClockUpdate()
383 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; in SystemCoreClockUpdate()
394 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; in SystemCoreClockUpdate()
395 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; in SystemCoreClockUpdate()
632 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | in SetSysClockTo24()
736 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | in SetSysClockTo36()
831 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | in SetSysClockTo48()
[all …]
|
| /bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/src/ |
| A D | hk32f0xx_syscfg.c | 74 SYSCFG->CFGR2 |= (uint32_t) SYSCFG_CFGR2_SRAM_PE; in SYSCFG_DeInit()
310 SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break; in SYSCFG_BreakConfig()
328 if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET) in SYSCFG_GetFlagStatus()
354 SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag; in SYSCFG_ClearFlag()
|
| A D | hk32f0xx_rcc.c | 142 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; in RCC_DeInit()
526 tmpreg = RCC->CFGR2; in RCC_PREDIV1Config()
532 RCC->CFGR2 = tmpreg; in RCC_PREDIV1Config()
998 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; in RCC_GetClocksFreq()
|
| A D | hk32f0xx_adc.c | 237 ADCx->CFGR2 = (uint32_t)ADC_ClockMode; in ADC_ClockModeConfig()
264 ADCx->CFGR2 |= (uint32_t)ADC_JitterOff; in ADC_JitterCmd()
269 ADCx->CFGR2 &= (uint32_t)(~ADC_JitterOff); in ADC_JitterCmd()
|
| /bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ |
| A D | ft32f0xx_syscfg.c | 40 SYSCFG->CFGR2 |= 0; in SYSCFG_DeInit()
209 SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break; in SYSCFG_BreakConfig()
|
| A D | ft32f0xx_rcc.c | 71 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; in RCC_DeInit()
468 tmpreg = RCC->CFGR2; in RCC_PREDIV1Config()
474 RCC->CFGR2 = tmpreg; in RCC_PREDIV1Config()
870 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; in RCC_GetClocksFreq()
|
| A D | ft32f0xx_adc.c | 175 ADCx->CFGR2 = (uint32_t)ADC_ClockMode; in ADC_ClockModeConfig()
202 ADCx->CFGR2 |= (uint32_t)ADC_JitterOff; in ADC_JitterCmd()
207 ADCx->CFGR2 &= (uint32_t)(~ADC_JitterOff); in ADC_JitterCmd()
|
| /bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Source/ |
| A D | system_hk32f0xx.c | 157 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; in SystemInit()
235 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV_1) + 1; in SystemCoreClockUpdate()
|
| /bsp/stm32/stm32u575-st-nucleo/board/CubeMX_Config/Src/ |
| A D | system_stm32u5xx.c | 206 RCC->CFGR2 = 0U; in SystemInit()
345 tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; in SystemCoreClockUpdate()
|
| /bsp/stm32/stm32u585-iot02a/board/CubeMX_Config/Src/ |
| A D | system_stm32u5xx.c | 206 RCC->CFGR2 = 0U; in SystemInit()
345 tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; in SystemCoreClockUpdate()
|
| /bsp/stm32/stm32h503-st-nucleo/board/CubeMX_Config/Src/ |
| A D | system_stm32h5xx.c | 214 RCC->CFGR2 = 0U; in SystemInit()
384 tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; in SystemCoreClockUpdate()
|
| /bsp/stm32/stm32h563-st-nucleo/board/CubeMX_Config/Src/ |
| A D | system_stm32h5xx.c | 214 RCC->CFGR2 = 0U; in SystemInit()
384 tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; in SystemCoreClockUpdate()
|
| /bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/ |
| A D | hal_eth.c | 123 SYSCFG->CFGR2 &= ~(1 << 21); in ETH_Init()
128 SYSCFG->CFGR2 |= 1 << 21; in ETH_Init()
133 SYSCFG->CFGR2 &= ~(1 << 21); in ETH_Init()
138 SYSCFG->CFGR2 |= 1 << 21; in ETH_Init()
145 SYSCFG->CFGR2 &= ~(1 << 21); in ETH_Init()
148 SYSCFG->CFGR2 |= 1 << 21; in ETH_Init()
|
| /bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/ |
| A D | system_ft32f0xx.c | 145 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; in SystemInit()
223 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; in SystemCoreClockUpdate()
|
| /bsp/mm32f327x/Libraries/MM32F327x/Include/ |
| A D | reg_syscfg.h | 62 …__IO u32 CFGR2; ///< SYSCFG configurat… member
|
| A D | reg_exti.h | 59 …__IO u32 CFGR2; ///< configuration reg… member
|
| A D | reg_rcc.h | 79 …__IO u32 CFGR2; ///< System Configurat… member
|
| /bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/ |
| A D | fm33lg0xx.h | 855 …__IO uint32_t CFGR2; /*!< ADC Config Register2, … member
890 …__IO uint32_t CFGR2; /*!< PGL Config Register2, … member
|
| /bsp/fm33lc026/libraries/FM/FM33xx/Include/ |
| A D | fm33lg0xx.h | 855 …__IO uint32_t CFGR2; /*!< ADC Config Register2, … member
890 …__IO uint32_t CFGR2; /*!< PGL Config Register2, … member
|
| /bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/ |
| A D | ft32f030x6.h | 189 …__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Addre… member
357 …__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address… member
486 …__IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Addres… member
|
| A D | ft32f030x8.h | 220 …__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Addre… member
388 …__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address… member
517 …__IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Addres… member
|
| A D | ft32f072x8.h | 227 …__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Addre… member
403 …__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address… member
532 …__IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Addres… member
|
| A D | ft32f032x8.h | 220 …__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Addre… member
397 …__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address… member
526 …__IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Addres… member
|