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Searched refs:CHANNEL (Results 1 – 25 of 139) sorted by relevance

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/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/
A Dht32f65xxx_66xxx_adc.h97 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1)… argument
98 … ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \
99 … ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \
100 … ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \
101 … ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \
106 #define IS_ADC_INPUT_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1)… argument
107 … ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \
131 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1)…
141 #define IS_ADC_INPUT_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1)…
163 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1)…
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A Dht32f5xxxx_exti.h115 #define IS_EXTI_CHANNEL(CHANNEL) ((CHANNEL == EXTI_CHANNEL_0) || \ argument
116 (CHANNEL == EXTI_CHANNEL_1) || \
117 (CHANNEL == EXTI_CHANNEL_2) || \
123 IS_CHANNEL_8(CHANNEL) || \
124 IS_CHANNEL_9(CHANNEL) || \
125 IS_CHANNEL_10(CHANNEL) || \
126 IS_CHANNEL_11(CHANNEL) || \
127 IS_CHANNEL_12(CHANNEL) || \
128 IS_CHANNEL_13(CHANNEL) || \
129 IS_CHANNEL_14(CHANNEL) || \
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A Dht32f5xxxx_adc.h76 #define IS_ADC_CHANNEL1(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1)… argument
77 … ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \
78 … ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \
79 ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7))
84 #define IS_ADC_CHANNEL2(CHANNEL) (((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9)) argument
90 #define IS_ADC_CHANNEL2(CHANNEL) (((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9)…
91 … ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11))
101 #define IS_ADC_CHANNEL3(CHANNEL) (((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_1… argument
102 … ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15))
302 #define IS_ADC_CHANNEL(CHANNEL) (IS_ADC_CHANNEL1(CHANNEL) || \ argument
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/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_hal_adc.h1073 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ argument
1074 ((CHANNEL) == ADC_CHANNEL_1) || \
1075 ((CHANNEL) == ADC_CHANNEL_2) || \
1076 ((CHANNEL) == ADC_CHANNEL_3) || \
1077 ((CHANNEL) == ADC_CHANNEL_4) || \
1078 ((CHANNEL) == ADC_CHANNEL_5) || \
1099 ((CHANNEL) == ADC_CHANNEL_26) )
1102 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ argument
1133 ((CHANNEL) == ADC_CHANNEL_31) )
1147 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ argument
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/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/
A Dstm32l1xx_ll_dma.c78 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ argument
79 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
80 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
81 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
82 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
83 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
84 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
93 ((CHANNEL) == LL_DMA_CHANNEL_7))))
95 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ argument
108 ((CHANNEL) == LL_DMA_CHANNEL_5))))
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/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/
A Dht32f1xxxx_adc.h85 #define IS_ADC_CHANNEL12_15(CHANNEL) (((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_1… argument
86 … ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15))
102 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH… argument
110 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1…
111 … ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \
112 … ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \
113 … ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \
114 … ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \
121 #define IS_ADC_INPUT_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1… argument
124 … ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7))
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A Dht32f1xxxx_exti.h87 #define IS_EXTI_CHANNEL(CHANNEL) ((CHANNEL == EXTI_CHANNEL_0) || \ argument
88 (CHANNEL == EXTI_CHANNEL_1) || \
89 (CHANNEL == EXTI_CHANNEL_2) || \
90 (CHANNEL == EXTI_CHANNEL_3) || \
91 (CHANNEL == EXTI_CHANNEL_4) || \
92 (CHANNEL == EXTI_CHANNEL_5) || \
93 (CHANNEL == EXTI_CHANNEL_6) || \
94 (CHANNEL == EXTI_CHANNEL_7) || \
95 (CHANNEL == EXTI_CHANNEL_8) || \
96 (CHANNEL == EXTI_CHANNEL_9) || \
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/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_acmp_drv.h139 ptr->CHANNEL[ch].DMAEN = (ptr->CHANNEL[ch].DMAEN & ~mask) in acmp_channel_dma_request_enable()
158 ptr->CHANNEL[ch].IRQEN = (ptr->CHANNEL[ch].IRQEN & ~mask) in acmp_channel_enable_irq()
173 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_DACEN_MASK) in acmp_channel_enable_dac()
188 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_HPMODE_MASK) in acmp_channel_enable_hpmode()
201 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_HYST_MASK) in acmp_channel_set_hyst()
216 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_CMPEN_MASK) in acmp_channel_enable_cmp()
231 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_CMPOEN_MASK) in acmp_channel_enable_cmp_output()
261 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_WINEN_MASK) in acmp_channel_enable_cmp_window_mode()
276 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_OPOL_MASK) in acmp_channel_invert_output()
304 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_SYNCEN_MASK) in acmp_channel_enable_sync()
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A Dhpm_gptmr_drv.h143 ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR in gptmr_channel_enable()
156 ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CNTRST_MASK; in gptmr_channel_reset_count()
175 ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CNTUPT_MASK; in gptmr_channel_update_count()
189 ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR in gptmr_channel_select_synci_valid_edge()
207 ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR in gptmr_channel_enable_dma_request()
317 ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CEN_MASK; in gptmr_start_counter()
328 ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CEN_MASK; in gptmr_stop_counter()
362 …ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR & ~GPTMR_CHANNEL_CR_CAPMODE_MASK) | GPTMR_C… in gptmr_channel_set_capmode()
402 return ptr->CHANNEL[ch_index].RLD; in gptmr_channel_get_reload()
468 …ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR & ~GPTMR_CHANNEL_CR_CNT_MODE_MASK) | GPTMR_… in gptmr_channel_set_counter_mode()
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/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/
A Dtsc_config.h411 #define CHANNEL (1) /*!< Channel IO */ macro
419 #define TOUCH_TSC_GROUP1_IO2 CHANNEL /*!< PA1 */
420 #define TOUCH_TSC_GROUP1_IO3 CHANNEL /*!< PA2 */
424 #define TOUCH_TSC_GROUP2_IO2 CHANNEL /*!< PA5 */
425 #define TOUCH_TSC_GROUP2_IO3 CHANNEL /*!< PA6 */
426 #define TOUCH_TSC_GROUP2_IO4 CHANNEL /*!< PA7 */
430 #define TOUCH_TSC_GROUP3_IO3 CHANNEL /*!< PB1 */
431 #define TOUCH_TSC_GROUP3_IO4 CHANNEL /*!< PB2 */
435 #define TOUCH_TSC_GROUP4_IO3 CHANNEL /*!< PA11 */
436 #define TOUCH_TSC_GROUP4_IO4 CHANNEL /*!< PA12 */
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/bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/inc/
A DHAL_adc.h207 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ argument
208 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
209 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
210 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
211 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_All))
246 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ argument
247 ((CHANNEL) == ADC_InjectedChannel_2) || \
248 ((CHANNEL) == ADC_InjectedChannel_3) || \
249 ((CHANNEL) == ADC_InjectedChannel_4) || \
250 ((CHANNEL) == ADC_InjectedChannel_5) || \
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/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/
A DHAL_adc.h199 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ argument
200 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
201 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
202 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
203 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_All))
238 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ argument
239 ((CHANNEL) == ADC_InjectedChannel_2) || \
240 ((CHANNEL) == ADC_InjectedChannel_3) || \
241 ((CHANNEL) == ADC_InjectedChannel_4) || \
242 ((CHANNEL) == ADC_InjectedChannel_5) || \
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/bsp/frdm-k64f/device/MK64F12/
A Dfsl_pit.h156 base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; in PIT_SetTimerChainMode()
160 base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; in PIT_SetTimerChainMode()
183 base->CHANNEL[channel].TCTRL |= mask; in PIT_EnableInterrupts()
196 base->CHANNEL[channel].TCTRL &= ~mask; in PIT_DisableInterrupts()
210 return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK); in PIT_GetEnabledInterrupts()
231 return (base->CHANNEL[channel].TFLG & PIT_TFLG_TIF_MASK); in PIT_GetStatusFlags()
244 base->CHANNEL[channel].TFLG = mask; in PIT_ClearStatusFlags()
270 base->CHANNEL[channel].LDVAL = count; in PIT_SetTimerPeriod()
288 return base->CHANNEL[channel].CVAL; in PIT_GetCurrentTimerCount()
310 base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; in PIT_StartTimer()
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/bsp/tkm32F499/Libraries/Hal_lib/inc/
A DHAL_adc.h208 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ argument
209 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
210 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
211 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
212 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_All))
263 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ argument
264 ((CHANNEL) == ADC_InjectedChannel_2) || \
265 ((CHANNEL) == ADC_InjectedChannel_3) || \
266 ((CHANNEL) == ADC_InjectedChannel_4) || \
267 ((CHANNEL) == ADC_InjectedChannel_5) || \
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/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/inc/
A Dhk32f0xx_adc.h217 #define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0) || \ argument
218 ((CHANNEL) == ADC_AnalogWatchdog_Channel_1) || \
219 ((CHANNEL) == ADC_AnalogWatchdog_Channel_2) || \
220 ((CHANNEL) == ADC_AnalogWatchdog_Channel_3) || \
221 ((CHANNEL) == ADC_AnalogWatchdog_Channel_4) || \
222 ((CHANNEL) == ADC_AnalogWatchdog_Channel_5) || \
223 ((CHANNEL) == ADC_AnalogWatchdog_Channel_6) || \
224 ((CHANNEL) == ADC_AnalogWatchdog_Channel_7) || \
225 ((CHANNEL) == ADC_AnalogWatchdog_Channel_8) || \
235 ((CHANNEL) == ADC_AnalogWatchdog_Channel_18))
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/bsp/airm2m/air32f103/libraries/AIR32F10xLib/inc/
A Dair32f10x_adc.h174 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ argument
175 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
176 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
177 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
178 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
179 ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
180 ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
181 ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
182 ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
256 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ argument
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/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/
A Dald_dma.c226 CLEAR_BIT(DMA->CHANNEL[i].CON, DMA_CON_CHEN_MSK); in ald_dma_reset()
227 WRITE_REG(DMA->CHANNEL[i].CON, 0x0); in ald_dma_reset()
228 WRITE_REG(DMA->CHANNEL[i].SAR, 0x0); in ald_dma_reset()
229 WRITE_REG(DMA->CHANNEL[i].DAR, 0x0); in ald_dma_reset()
230 WRITE_REG(DMA->CHANNEL[i].NDT, 0x0); in ald_dma_reset()
327 SET_BIT(DMA->CHANNEL[channel].CON, DMA_CON_CHEN_MSK); in ald_dma_channel_config()
331 CLEAR_BIT(DMA->CHANNEL[channel].CON, DMA_CON_CHEN_MSK); in ald_dma_channel_config()
332 WRITE_REG(DMA->CHANNEL[channel].CON, 0x0); in ald_dma_channel_config()
333 WRITE_REG(DMA->CHANNEL[channel].SAR, 0x0); in ald_dma_channel_config()
334 WRITE_REG(DMA->CHANNEL[channel].DAR, 0x0); in ald_dma_channel_config()
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/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/
A DHAL_TIMER.h71 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ argument
73 (((CHANNEL) == TIM_CHANNEL_1) || \
74 ((CHANNEL) == TIM_CHANNEL_2) || \
75 ((CHANNEL) == TIM_CHANNEL_3) || \
79 (((CHANNEL) == TIM_CHANNEL_1) || \
80 ((CHANNEL) == TIM_CHANNEL_2) || \
81 ((CHANNEL) == TIM_CHANNEL_3) || \
85 (((CHANNEL) == TIM_CHANNEL_1) || \
86 ((CHANNEL) == TIM_CHANNEL_2) || \
107 ((CHANNEL) == TIM_CHANNEL_1) ) )
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/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/
A Dn32l43x_adc.h166 #define IsAdcChannel(CHANNEL) … argument
167 …(((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == AD…
168 …|| ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == …
169 …|| ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) ==…
170 …|| ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) …
171 || ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18))
228 #define IsAdcInjCh(CHANNEL) … argument
229 …(((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3) …
230 || ((CHANNEL) == ADC_INJ_CH_4))
/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/
A Dn32l40x_adc.h166 #define IsAdcChannel(CHANNEL) … argument
167 …(((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == AD…
168 …|| ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == …
169 …|| ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) ==…
170 …|| ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) …
171 || ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18))
228 #define IsAdcInjCh(CHANNEL) … argument
229 …(((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3) …
230 || ((CHANNEL) == ADC_INJ_CH_4))
/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/
A Dn32g43x_adc.h166 #define IsAdcChannel(CHANNEL) … argument
167 …(((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == AD…
168 …|| ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == …
169 …|| ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) ==…
170 …|| ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) …
171 || ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18))
228 #define IsAdcInjCh(CHANNEL) … argument
229 …(((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3) …
230 || ((CHANNEL) == ADC_INJ_CH_4))
/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/
A Dft32f0xx_adc.h216 #define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0) || \ argument
217 ((CHANNEL) == ADC_AnalogWatchdog_Channel_1) || \
218 ((CHANNEL) == ADC_AnalogWatchdog_Channel_2) || \
219 ((CHANNEL) == ADC_AnalogWatchdog_Channel_3) || \
220 ((CHANNEL) == ADC_AnalogWatchdog_Channel_4) || \
221 ((CHANNEL) == ADC_AnalogWatchdog_Channel_5) || \
222 ((CHANNEL) == ADC_AnalogWatchdog_Channel_6) || \
223 ((CHANNEL) == ADC_AnalogWatchdog_Channel_7) || \
234 ((CHANNEL) == ADC_AnalogWatchdog_Channel_18))
309 …#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFC00000) == (u… argument
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/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_evsys_d51.h993 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit()
1002 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit()
1005 ((EvsysChannel *)hw)->CHANNEL.reg = tmp; in hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit()
1033 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_get_CHANNEL_ONDEMAND_bit()
1042 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_write_CHANNEL_ONDEMAND_bit()
1045 ((EvsysChannel *)hw)->CHANNEL.reg = tmp; in hri_evsyschannel_write_CHANNEL_ONDEMAND_bit()
1074 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_get_CHANNEL_EVGEN_bf()
1083 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_write_CHANNEL_EVGEN_bf()
1086 ((EvsysChannel *)hw)->CHANNEL.reg = tmp; in hri_evsyschannel_write_CHANNEL_EVGEN_bf()
1107 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_read_CHANNEL_EVGEN_bf()
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/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_evsys_d51.h993 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit()
1002 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit()
1005 ((EvsysChannel *)hw)->CHANNEL.reg = tmp; in hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit()
1033 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_get_CHANNEL_ONDEMAND_bit()
1042 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_write_CHANNEL_ONDEMAND_bit()
1045 ((EvsysChannel *)hw)->CHANNEL.reg = tmp; in hri_evsyschannel_write_CHANNEL_ONDEMAND_bit()
1074 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_get_CHANNEL_EVGEN_bf()
1083 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_write_CHANNEL_EVGEN_bf()
1086 ((EvsysChannel *)hw)->CHANNEL.reg = tmp; in hri_evsyschannel_write_CHANNEL_EVGEN_bf()
1107 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_read_CHANNEL_EVGEN_bf()
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/bsp/microchip/same54/bsp/hri/
A Dhri_evsys_e54.h993 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit()
1002 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit()
1005 ((EvsysChannel *)hw)->CHANNEL.reg = tmp; in hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit()
1033 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_get_CHANNEL_ONDEMAND_bit()
1042 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_write_CHANNEL_ONDEMAND_bit()
1045 ((EvsysChannel *)hw)->CHANNEL.reg = tmp; in hri_evsyschannel_write_CHANNEL_ONDEMAND_bit()
1074 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_get_CHANNEL_EVGEN_bf()
1083 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_write_CHANNEL_EVGEN_bf()
1086 ((EvsysChannel *)hw)->CHANNEL.reg = tmp; in hri_evsyschannel_write_CHANNEL_EVGEN_bf()
1107 tmp = ((EvsysChannel *)hw)->CHANNEL.reg; in hri_evsyschannel_read_CHANNEL_EVGEN_bf()
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