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Searched refs:CHCTRLB (Results 1 – 14 of 14) sorted by relevance

/bsp/ck802/libraries/common/dmac/
A Dck_dmac.c60 uint32_t temp = addr->CHCTRLB; in ck_dma_set_transfertype()
73 addr->CHCTRLB = temp; in ck_dma_set_transfertype()
128 uint32_t temp = addr->CHCTRLB; in ck_dma_set_handshaking()
131 addr->CHCTRLB = temp; in ck_dma_set_handshaking()
142 addr->CHCTRLB &= 0xffffe1ff; in ck_dma_assign_hdhs_interface()
143 addr->CHCTRLB |= (device << 9); in ck_dma_assign_hdhs_interface()
465 addr->CHCTRLB |= CK_DMA_INT_EN; // interrupt enable in csi_dma_start()
492 addr->CHCTRLB &= ~CK_DMA_INT_EN; // interrupt disable in csi_dma_stop()
A Dck_dmac.h63 __IOM uint32_t CHCTRLB; /* offset: 0x0C (R/W) Channel Control Register B */ member
/bsp/microchip/saml10/bsp/hri/
A Dhri_dmac_l10.h2935 tmp = ((Dmac *)hw)->CHCTRLB.reg; in hri_dmac_get_CHCTRLB_EVIE_bit()
2944 tmp = ((Dmac *)hw)->CHCTRLB.reg; in hri_dmac_write_CHCTRLB_EVIE_bit()
2947 ((Dmac *)hw)->CHCTRLB.reg = tmp; in hri_dmac_write_CHCTRLB_EVIE_bit()
2975 tmp = ((Dmac *)hw)->CHCTRLB.reg; in hri_dmac_get_CHCTRLB_EVOE_bit()
2984 tmp = ((Dmac *)hw)->CHCTRLB.reg; in hri_dmac_write_CHCTRLB_EVOE_bit()
2987 ((Dmac *)hw)->CHCTRLB.reg = tmp; in hri_dmac_write_CHCTRLB_EVOE_bit()
3015 tmp = ((Dmac *)hw)->CHCTRLB.reg; in hri_dmac_get_CHCTRLB_EVACT_bf()
3024 tmp = ((Dmac *)hw)->CHCTRLB.reg; in hri_dmac_write_CHCTRLB_EVACT_bf()
3027 ((Dmac *)hw)->CHCTRLB.reg = tmp; in hri_dmac_write_CHCTRLB_EVACT_bf()
3048 tmp = ((Dmac *)hw)->CHCTRLB.reg; in hri_dmac_read_CHCTRLB_EVACT_bf()
[all …]
/bsp/microchip/samc21/bsp/hri/
A Dhri_dmac_c21.h3155 tmp = ((Dmac *)hw)->CHCTRLB.reg; in hri_dmac_get_CHCTRLB_EVIE_bit()
3164 tmp = ((Dmac *)hw)->CHCTRLB.reg; in hri_dmac_write_CHCTRLB_EVIE_bit()
3167 ((Dmac *)hw)->CHCTRLB.reg = tmp; in hri_dmac_write_CHCTRLB_EVIE_bit()
3195 tmp = ((Dmac *)hw)->CHCTRLB.reg; in hri_dmac_get_CHCTRLB_EVOE_bit()
3204 tmp = ((Dmac *)hw)->CHCTRLB.reg; in hri_dmac_write_CHCTRLB_EVOE_bit()
3207 ((Dmac *)hw)->CHCTRLB.reg = tmp; in hri_dmac_write_CHCTRLB_EVOE_bit()
3235 tmp = ((Dmac *)hw)->CHCTRLB.reg; in hri_dmac_get_CHCTRLB_EVACT_bf()
3244 tmp = ((Dmac *)hw)->CHCTRLB.reg; in hri_dmac_write_CHCTRLB_EVACT_bf()
3247 ((Dmac *)hw)->CHCTRLB.reg = tmp; in hri_dmac_write_CHCTRLB_EVACT_bf()
3268 tmp = ((Dmac *)hw)->CHCTRLB.reg; in hri_dmac_read_CHCTRLB_EVACT_bf()
[all …]
/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/
A Ddma.c174 DMAC->CHCTRLB.reg = temp_CHCTRLB_reg; in _dma_set_config()
533 DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND; in dma_suspend_job()
566 DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME; in dma_resume_job()
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_dmac_d51.h5292 tmp = ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_get_CHCTRLB_CMD_bf()
5301 tmp = ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_write_CHCTRLB_CMD_bf()
5304 ((DmacChannel *)hw)->CHCTRLB.reg = tmp; in hri_dmacchannel_write_CHCTRLB_CMD_bf()
5325 tmp = ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_read_CHCTRLB_CMD_bf()
5333 ((DmacChannel *)hw)->CHCTRLB.reg |= mask; in hri_dmacchannel_set_CHCTRLB_reg()
5340 tmp = ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_get_CHCTRLB_reg()
5348 ((DmacChannel *)hw)->CHCTRLB.reg = data; in hri_dmacchannel_write_CHCTRLB_reg()
5355 ((DmacChannel *)hw)->CHCTRLB.reg &= ~mask; in hri_dmacchannel_clear_CHCTRLB_reg()
5362 ((DmacChannel *)hw)->CHCTRLB.reg ^= mask; in hri_dmacchannel_toggle_CHCTRLB_reg()
5368 return ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_read_CHCTRLB_reg()
[all …]
/bsp/microchip/same54/bsp/hri/
A Dhri_dmac_e54.h5292 tmp = ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_get_CHCTRLB_CMD_bf()
5301 tmp = ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_write_CHCTRLB_CMD_bf()
5304 ((DmacChannel *)hw)->CHCTRLB.reg = tmp; in hri_dmacchannel_write_CHCTRLB_CMD_bf()
5325 tmp = ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_read_CHCTRLB_CMD_bf()
5333 ((DmacChannel *)hw)->CHCTRLB.reg |= mask; in hri_dmacchannel_set_CHCTRLB_reg()
5340 tmp = ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_get_CHCTRLB_reg()
5348 ((DmacChannel *)hw)->CHCTRLB.reg = data; in hri_dmacchannel_write_CHCTRLB_reg()
5355 ((DmacChannel *)hw)->CHCTRLB.reg &= ~mask; in hri_dmacchannel_clear_CHCTRLB_reg()
5362 ((DmacChannel *)hw)->CHCTRLB.reg ^= mask; in hri_dmacchannel_toggle_CHCTRLB_reg()
5368 return ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_read_CHCTRLB_reg()
[all …]
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_dmac_d51.h5292 tmp = ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_get_CHCTRLB_CMD_bf()
5301 tmp = ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_write_CHCTRLB_CMD_bf()
5304 ((DmacChannel *)hw)->CHCTRLB.reg = tmp; in hri_dmacchannel_write_CHCTRLB_CMD_bf()
5325 tmp = ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_read_CHCTRLB_CMD_bf()
5333 ((DmacChannel *)hw)->CHCTRLB.reg |= mask; in hri_dmacchannel_set_CHCTRLB_reg()
5340 tmp = ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_get_CHCTRLB_reg()
5348 ((DmacChannel *)hw)->CHCTRLB.reg = data; in hri_dmacchannel_write_CHCTRLB_reg()
5355 ((DmacChannel *)hw)->CHCTRLB.reg &= ~mask; in hri_dmacchannel_clear_CHCTRLB_reg()
5362 ((DmacChannel *)hw)->CHCTRLB.reg ^= mask; in hri_dmacchannel_toggle_CHCTRLB_reg()
5368 return ((DmacChannel *)hw)->CHCTRLB.reg; in hri_dmacchannel_read_CHCTRLB_reg()
[all …]
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/
A Ddmac.h1059 __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ member
/bsp/microchip/samc21/bsp/samc21/include/component/
A Ddmac.h1041 __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ member
/bsp/microchip/saml10/bsp/include/component/
A Ddmac.h1143 …__IO DMAC_CHCTRLB_Type CHCTRLB; /**< Offset: 0x44 (R/W 32) Channel Control B … member
/bsp/microchip/same54/bsp/include/component/
A Ddmac.h1356 …__IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x04 (R/W 8) Channel n Control B … member
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Ddmac.h1356 …__IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x04 (R/W 8) Channel n Control B … member
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Ddmac.h1356 …__IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x04 (R/W 8) Channel n Control B … member

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