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Searched refs:CHN_NUM (Results 1 – 15 of 15) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/lowlevel_v2x/
A Dde_feat.h43 #define CHN_NUM 4 macro
79 #define CHN_NUM 4 macro
103 #define CHN_NUM 2 macro
126 #define CHN_NUM 4 macro
156 #define CHN_NUM 4 macro
187 #define CHN_NUM 4 macro
237 #define CHN_NUM 4 macro
269 #define CHN_NUM 4 macro
364 #define CHN_NUM 4 macro
383 #define CHN_NUM 4 macro
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A Dde_bws_type.h28 extern unsigned int *g_hist[DE_NUM][CHN_NUM];
29 extern unsigned int *g_hist_p[DE_NUM][CHN_NUM];
30 extern unsigned int g_sum[DE_NUM][CHN_NUM];
31 extern struct __hist_status_t *g_hist_status[DE_NUM][CHN_NUM];
A Dde_hal.c336 unsigned char premul[CHN_NUM][LAYER_MAX_NUM_PER_CHN], format[CHN_NUM], in de_al_lyr_apply()
337 premode[CHN_NUM], zoder[CHN_NUM] = { 0, 1}, pen[CHN_NUM]; in de_al_lyr_apply()
338 unsigned int ovlw[CHN_NUM], ovlh[CHN_NUM]; in de_al_lyr_apply()
340 struct de_rect layer[CHN_NUM][LAYER_MAX_NUM_PER_CHN], bld_rect[CHN_NUM]; in de_al_lyr_apply()
343 bool chn_used[CHN_NUM] = { false }, chn_zorder_cfg[CHN_NUM] = { in de_al_lyr_apply()
344 false}, chn_dirty[CHN_NUM] = { in de_al_lyr_apply()
346 bool chn_is_yuv[CHN_NUM] = { false }; in de_al_lyr_apply()
347 enum de_color_space cs[CHN_NUM]; in de_al_lyr_apply()
350 unsigned int pipe_sel[CHN_NUM] = { 0 }; in de_al_lyr_apply()
351 struct de_rect pipe_rect[CHN_NUM] = { {0} }; in de_al_lyr_apply()
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A Dde_enhance.h46 extern struct __ce_status_t *g_ce_status[DE_NUM][CHN_NUM];
56 extern struct __hist_status_t *g_hist_status[DE_NUM][CHN_NUM];
57 extern struct __ce_status_t *g_ce_status[DE_NUM][CHN_NUM];
58 extern unsigned int *g_hist[DE_NUM][CHN_NUM];
59 extern unsigned int g_sum[DE_NUM][CHN_NUM];
60 extern unsigned int *g_hist_p[DE_NUM][CHN_NUM];
A Dde_fce_type.h56 extern unsigned int *g_hist[DE_NUM][CHN_NUM];
57 extern unsigned int *g_hist_p[DE_NUM][CHN_NUM];
58 extern unsigned int g_sum[DE_NUM][CHN_NUM];
A Dde_peak.c27 static volatile struct __peak_reg_t *peak_dev[DE_NUM][CHN_NUM];
28 static struct de_reg_blocks peak_block[DE_NUM][CHN_NUM];
29 static struct de_reg_blocks peak_gain_block[DE_NUM][CHN_NUM];
A Dde_fce.c26 static volatile struct __fce_reg_t *fce_dev[DE_NUM][CHN_NUM];
28 static struct de_reg_blocks fce_para_block[DE_NUM][CHN_NUM];
29 static struct de_reg_blocks fce_celut_block[DE_NUM][CHN_NUM];
30 static struct de_reg_blocks fce_hist_block[DE_NUM][CHN_NUM];
32 static uintptr_t fce_hw_base[DE_NUM][CHN_NUM] = { {0} };
34 struct __hist_status_t *g_hist_status[DE_NUM][CHN_NUM];
37 struct __ce_status_t *g_ce_status[DE_NUM][CHN_NUM];
38 static unsigned char *g_celut[DE_NUM][CHN_NUM];
39 static struct hist_data *hist_res[DE_NUM][CHN_NUM];
A Dde_bws.c30 static volatile struct __bws_reg_t *bws_dev[DE_NUM][CHN_NUM];
31 static struct de_reg_blocks bws_block[DE_NUM][CHN_NUM];
32 static struct de_reg_blocks bws_para_block[DE_NUM][CHN_NUM];
34 static uintptr_t bws_hw_base[DE_NUM][CHN_NUM] = { {0} };
37 static struct __bws_status_t *g_bws_status[DE_NUM][CHN_NUM];
A Dde_ase.c24 static volatile struct __ase_reg_t *ase_dev[DE_NUM][CHN_NUM];
25 static struct de_reg_blocks ase_block[DE_NUM][CHN_NUM];
A Dde_fcc.c28 static volatile struct __fcc_reg_t *fcc_dev[DE_NUM][CHN_NUM];
29 static struct de_reg_blocks fcc_para_block[DE_NUM][CHN_NUM];
A Dde_ccsc.c38 static volatile struct __csc_reg_t *ccsc_dev[DE_NUM][CHN_NUM];
39 static volatile struct __icsc_reg_t *icsc_dev[DE_NUM][CHN_NUM];
40 static struct de_reg_blocks csc_block[DE_NUM][CHN_NUM];
41 static struct de_reg_blocks icsc_block[DE_NUM][CHN_NUM];
44 static unsigned int vep_support[DE_NUM][CHN_NUM];
A Dde_lti.c26 static volatile struct __lti_reg_t *lti_dev[DE_NUM][CHN_NUM];
27 static struct de_reg_blocks lti_block[DE_NUM][CHN_NUM];
A Dde_enhance.c50 unsigned int *g_hist[DE_NUM][CHN_NUM];
51 unsigned int *g_hist_p[DE_NUM][CHN_NUM];
52 unsigned int g_sum[DE_NUM][CHN_NUM];
A Dde_rtmx.c38 ui_attr_block[DE_NUM][CHN_NUM - VI_CHN_NUM][LAYER_MAX_NUM_PER_CHN];
39 static struct de_reg_blocks ui_haddr_block[DE_NUM][CHN_NUM - VI_CHN_NUM];
40 static struct de_reg_blocks ui_size_block[DE_NUM][CHN_NUM - VI_CHN_NUM];
52 static struct de_reg_blocks ui_palette_block[DE_NUM][CHN_NUM - VI_CHN_NUM];
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/
A Dmbox.c25 #define CHN_NUM 4 macro
59 for (uint32_t i = 0U; i < CHN_NUM; i++) { in csi_mbox_init()
67 for (uint32_t i = 0U; i < CHN_NUM; i++) { in csi_mbox_init()
84 for (uint32_t i = 0U; i < CHN_NUM; i++) { in csi_mbox_uninit()
163 if (channel_id < CHN_NUM) { in csi_mbox_receive()

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