Searched refs:CLKCON0 (Results 1 – 4 of 4) sorted by relevance
270 CLKCON0 &= ~(BIT(2) | BIT(3)); //sysclk sel rc2m in set_sysclk_do()275 CLKCON0 &= ~(BIT(4) | BIT(5) | BIT(6)); //sys_pll select pll0out in set_sysclk_do()291 CLKCON0 &= ~(BIT(4) | BIT(5) | BIT(6)); in set_sysclk_do()292 CLKCON0 |= BIT(6); //spll select xosc26m_clk in set_sysclk_do()296 CLKCON0 |= BIT(3); //sysclk sel spll in set_sysclk_do()
174 CLKCON0 &= ~(7 << 23); in rt_hw_systick_init()175 CLKCON0 |= BIT(24); //tmr_inc select x26m_div_clk = 1M in rt_hw_systick_init()
144 CLKCON0 |= BIT(28); // enable adc clock in ab32_adc_init()
100 #define CLKCON0 SFR_RW (SFR0_BASE + 0x19*4) macro
Completed in 9 milliseconds