Home
last modified time | relevance | path

Searched refs:CLKCON2 (Results 1 – 4 of 4) sorted by relevance

/bsp/bluetrum/libraries/hal_libraries/bmsis/source/
A Dsystem_ab32vgx.c179 uint32_t clkcon2 = CLKCON2; in set_peripherals_clkdiv_safety()
202 CLKCON2 = clkcon2; in set_peripherals_clkdiv_safety()
209 uint32_t clkcon2 = CLKCON2; in set_peripherals_clkdiv()
254 CLKCON2 = clkcon2; in set_peripherals_clkdiv()
271 CLKCON2 &= ~(0x1f << 8); //reset spll div in set_sysclk_do()
295 CLKCON2 |= (spll_div << 8); in set_sysclk_do()
/bsp/bluetrum/ab32vg1-ab-prougen/board/
A Dboard.c172 CLKCON2 &= 0x00ffffff; in rt_hw_systick_init()
173 …CLKCON2 |= (25 << 24); //配置x26m_div_clk = 1M (timer, ir, fmam ...… in rt_hw_systick_init()
/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/
A Ddrv_sound.c40 CLKCON2 &= ~(BIT(4)| BIT(5) | BIT(6) | BIT(7)); in adpll_init()
50 CLKCON2 |= BIT(4) | BIT(7); //adpll_div = 10 in adpll_init()
54 CLKCON2 |= BIT(5) | BIT(7); //adpll_div = 11 in adpll_init()
/bsp/bluetrum/libraries/hal_libraries/bmsis/include/
A Dab32vg1.h175 #define CLKCON2 SFR_RW (SFR3_BASE + 0x2a*4) macro

Completed in 10 milliseconds