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Searched refs:CLKSEL (Results 1 – 25 of 40) sorted by relevance

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/bsp/synwit/libraries/SWM341_CSL/CMSIS/DeviceSupport/
A Dsystem_SWM341.c232 if(((SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) == 0) && in delay_3ms()
261 SYS->CLKSEL &= ~SYS_CLKSEL_CLK_Msk; in switchTo2M5Hz()
264 SYS->CLKSEL |= (1 << SYS_CLKSEL_CLK_DIVx_Pos); in switchTo2M5Hz()
287 SYS->CLKSEL &= ~SYS_CLKSEL_CLK_Msk; in switchTo5MHz()
290 SYS->CLKSEL |= (1 << SYS_CLKSEL_CLK_DIVx_Pos); in switchTo5MHz()
310 SYS->CLKSEL &= ~SYS_CLKSEL_CLK_Msk; in switchToXTAL()
327 SYS->CLKSEL &= ~SYS_CLKSEL_CLK_Msk; in switchToPLL()
344 SYS->CLKSEL &= ~SYS_CLKSEL_CLK_Msk; in switchTo32KHz()
347 SYS->CLKSEL &=~(1 << SYS_CLKSEL_CLK_DIVx_Pos); in switchTo32KHz()
365 SYS->CLKSEL &= ~SYS_CLKSEL_CLK_Msk; in switchToXTAL_32K()
[all …]
A DSWM341.h143 __IO uint32_t CLKSEL; //Clock Select member
/bsp/synwit/libraries/SWM320_CSL/CMSIS/DeviceSupport/
A Dsystem_SWM320.c81 if(SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) //SYS_CLK <= HFCK in SystemCoreClockUpdate()
83 if(SYS->CLKSEL & SYS_CLKSEL_HFCK_Msk) //HFCK <= XTAL in SystemCoreClockUpdate()
101 if(SYS->CLKSEL & SYS_CLKSEL_LFCK_Msk) //LFCK <= PLL in SystemCoreClockUpdate()
188 if(((SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) == 0) && in delay_3ms()
189 ((SYS->CLKSEL & SYS_CLKSEL_LFCK_Msk) == 0)) //32KHz in delay_3ms()
206 SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC in switchCLK_20MHz()
207 SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK in switchCLK_20MHz()
217 SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC in switchCLK_40MHz()
229 SYS->CLKSEL &= ~SYS_CLKSEL_LFCK_Msk; //LFCK <= LRC in switchCLK_32KHz()
240 SYS->CLKSEL |= (1 << SYS_CLKSEL_HFCK_Pos); //HFCK <= XTAL in switchCLK_XTAL()
[all …]
A DSWM320.h117 __IO uint32_t CLKSEL; //Clock Select member
/bsp/Vango/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/
A Dlib_clk.c118 MISC2->CLKSEL = 0; in CLK_ClockConfig()
229 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; in CLK_ClockConfig()
238 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; in CLK_ClockConfig()
251 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; in CLK_ClockConfig()
264 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; in CLK_ClockConfig()
270 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; in CLK_ClockConfig()
378 ahb_clksrc = MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL; in CLK_GetHCLKFreq()
604 CLK_ClkInitStruct->AHBSource = (uint32_t)(MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL); in CLK_GetClockConfig()
A Dlib_adc.c485 if ((MISC2->CLKSEL&MISC2_CLKSEL_CLKSEL) == MISC2_CLKSEL_CLKSEL_RTCCLK) in ADC_Cmd()
504 if ((MISC2->CLKSEL&MISC2_CLKSEL_CLKSEL) == MISC2_CLKSEL_CLKSEL_RTCCLK) in ADC_Cmd()
/bsp/Vango/v85xx/Libraries/VangoV85xx_standard_peripheral/Source/
A Dlib_clk.c119 MISC2->CLKSEL = 0; in CLK_ClockConfig()
241 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; in CLK_ClockConfig()
251 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; in CLK_ClockConfig()
265 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; in CLK_ClockConfig()
279 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; in CLK_ClockConfig()
285 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; in CLK_ClockConfig()
393 ahb_clksrc = MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL; in CLK_GetHCLKFreq()
564 CLK_ClkInitStruct->AHBSource = (uint32_t)(MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL); in CLK_GetClockConfig()
/bsp/synwit/libraries/SWM341_CSL/SWM341_StdPeriph_Driver/
A DSWM341_iofilt.c39 SYS->CLKSEL &= ~SYS_CLKSEL_IOFILT_Msk; in IOFILT_Init()
40 SYS->CLKSEL |= (0 << SYS_CLKSEL_IOFILT_Pos); //滤波器时钟源：HRC in IOFILT_Init()
A DSWM341_adc.c38 SYS->CLKSEL &= ~(SYS_CLKSEL_AD0_Msk | SYS_CLKSEL_AD0DIV_Msk); in ADC_Init()
39 SYS->CLKSEL |= (initStruct->clk_src << SYS_CLKSEL_AD0_Pos); in ADC_Init()
45 SYS->CLKSEL &= ~(SYS_CLKSEL_AD1_Msk | SYS_CLKSEL_AD1DIV_Msk); in ADC_Init()
46 SYS->CLKSEL |= (initStruct->clk_src << SYS_CLKSEL_AD1_Pos); in ADC_Init()
A DSWM341_sdio.c39 SYS->CLKSEL &= ~SYS_CLKSEL_SDIO_Msk; in SDIO_Init()
41 SYS->CLKSEL |= (2 << SYS_CLKSEL_SDIO_Pos); //SDCLK = SYSCLK / 4 in SDIO_Init()
43 SYS->CLKSEL |= (0 << SYS_CLKSEL_SDIO_Pos); //SDCLK = SYSCLK / 2 in SDIO_Init()
584 switch((SYS->CLKSEL & SYS_CLKSEL_SDIO_Msk) >> SYS_CLKSEL_SDIO_Pos) in calcSDCLKDiv()
622 SYS->CLKSEL &= ~SYS_CLKSEL_SDIO_Msk; in SDIO_IO_Init()
624 SYS->CLKSEL |= (2 << SYS_CLKSEL_SDIO_Pos); //SDCLK = SYSCLK / 4 in SDIO_IO_Init()
626 SYS->CLKSEL |= (0 << SYS_CLKSEL_SDIO_Pos); //SDCLK = SYSCLK / 2 in SDIO_IO_Init()
A DSWM341_rtc.c44 SYS->CLKSEL &= ~SYS_CLKSEL_RTC_Msk; in RTC_Init()
45 SYS->CLKSEL |= (initStruct->clksrc << SYS_CLKSEL_RTC_Pos); in RTC_Init()
/bsp/apollo2/libraries/drivers/hal/
A Dam_hal_stimer.c83 if ( (AM_BFR(CTIMER, STCFG, CLKSEL) == AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV16) || in am_hal_stimer_config()
84 (AM_BFR(CTIMER, STCFG, CLKSEL) == AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV256) ) in am_hal_stimer_config()
A Dam_hal_ctimer.c232 ui32TimerASrc = AM_BFR(CTIMER, STCFG, CLKSEL); in timers_use_hfrc()
/bsp/synwit/libraries/SWM341_drivers/
A Ddrv_sdio.c567 switch((SYS->CLKSEL & SYS_CLKSEL_SDIO_Msk) >> SYS_CLKSEL_SDIO_Pos) in swm_sdio_clock_get()
683 SYS->CLKSEL &= ~SYS_CLKSEL_SDIO_Msk; in swm_sdio_init()
685 SYS->CLKSEL |= (2 << SYS_CLKSEL_SDIO_Pos); //SDCLK = SYSCLK / 4 in swm_sdio_init()
687 SYS->CLKSEL |= (0 << SYS_CLKSEL_SDIO_Pos); //SDCLK = SYSCLK / 2 in swm_sdio_init()
/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/
A Dhc32l196_pcnt.c208 M0P_PCNT->CTRL_f.CLKSEL = InitStruct->Pcnt_Clk; in Pcnt_Init()
/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/
A Dpcnt.c132 M0P_PCNT->CR_f.CLKSEL = pstcPcntConfig->u8Clk; in PCNT_Init()
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/
A Di2s.h453 uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */ member
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Di2s.h558 uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */ member
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Di2s.h558 uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */ member
/bsp/microchip/same54/bsp/include/component/
A Di2s.h558 uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */ member
/bsp/Vango/v85xxp/Libraries/CMSIS/Vango/V85xxP/Include/
A Dtarget.h424 …__IOM uint32_t CLKSEL; /*!< (@ 0x00000004) Clock selection register. … member
/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA6M3AH.h2020 …__IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select … member
14834 …__IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select … member
18124 …__IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency … member
19278 …__IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency … member
/bsp/Vango/v85xx/Libraries/CMSIS/Vango/V85xx/Include/
A Dtarget.h493 …__IO uint32_t CLKSEL; /*!< Clock selection register, Address offse… member
/bsp/renesas/ra2l1-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h2557 …__IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select … member
8533 …__IOM uint32_t CLKSEL : 2; /*!< [5..4] Observation Clock Select … member
19765 …__IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select … member
23326 …__IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency … member
24388 …__IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency … member
26143 …__IOM uint32_t CLKSEL : 2; /*!< [1..0] ADCLK Clock Source Select … member
/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h2557 …__IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select … member
8533 …__IOM uint32_t CLKSEL : 2; /*!< [5..4] Observation Clock Select … member
19765 …__IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select … member
23326 …__IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency … member
24388 …__IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency … member
26143 …__IOM uint32_t CLKSEL : 2; /*!< [1..0] ADCLK Clock Source Select … member

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