Searched refs:CLK_PLL_DDR (Results 1 – 4 of 4) sorted by relevance
| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/sun8iw18p1/ |
| A D | clk_sun8iw18.h | 52 #define CLK_PLL_DDR (volatile uint32_t *)(CCU_REG_BASE + 0x0010) macro
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| A D | clk_sun8iw18.c | 573 SUNXI_CLK_FACTORS_INIT(pll_ddr, CLK_PLL_DDR, CLK_PLL_DDR, 28, CLK_PLL_DDR, 29);
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/sun8iw19p1/ |
| A D | clk_sun8iw19.h | 52 #define CLK_PLL_DDR (volatile uint32_t *)(CCU_REG_BASE + 0x0010) macro
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| A D | clk_sun8iw19.c | 778 SUNXI_CLK_FACTORS_INIT(pll_ddr, CLK_PLL_DDR, CLK_PLL_DDR, 28, CLK_PLL_DDR, 29);
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