Searched refs:CLK_PLL_DDRPAT (Results 1 – 4 of 4) sorted by relevance
| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/sun8iw18p1/ |
| A D | clk_sun8iw18.h | 59 #define CLK_PLL_DDRPAT (volatile uint32_t *)(CCU_REG_BASE + 0x0110) macro
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| A D | clk_sun8iw18.c | 565 … 0, 0, 1, 1, 0, 1, 0, 0, 0, 31, 24, 0, CLK_PLL_DDRPAT, 0xd1303333…
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/sun8iw19p1/ |
| A D | clk_sun8iw19.h | 60 #define CLK_PLL_DDRPAT (volatile uint32_t *)(CCU_REG_BASE + 0x0110) macro
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| A D | clk_sun8iw19.c | 769 … 0, 0, 1, 1, 0, 1, 0, 0, 0, 31, 24, 0, CLK_PLL_DDRPAT, 0xd1303333…
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Completed in 605 milliseconds