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Searched refs:CLK_PLL_PERIPH0 (Results 1 – 8 of 8) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/source/spi/platform/
A Dspi_sun8iw20.h60 #define SUNXI_CLK_PLL_SPI CLK_PLL_PERIPH0
/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/soc/
A Dsun20iw1.c115 CLK_PLL_PERIPH0,
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/
A Dccu-sun8iw20.h16 #define CLK_PLL_PERIPH0 5 macro
A Dccu-sun8iw20.c971 [CLK_PLL_PERIPH0] = &pll_periph0_clk.hw,
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/sun8iw18p1/
A Dclk_sun8iw18.h53 #define CLK_PLL_PERIPH0 (volatile uint32_t *)(CCU_REG_BASE + 0x0020) macro
A Dclk_sun8iw18.c574 SUNXI_CLK_FACTORS_INIT(pll_periph0, CLK_PLL_PERIPH0, CLK_PLL_PERIPH0, 28, CLK_PLL_PERIPH0, 29);
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/sun8iw19p1/
A Dclk_sun8iw19.h53 #define CLK_PLL_PERIPH0 (volatile uint32_t *)(CCU_REG_BASE + 0x0020) macro
A Dclk_sun8iw19.c779 SUNXI_CLK_FACTORS_INIT(pll_periph0, CLK_PLL_PERIPH0, CLK_PLL_PERIPH0, 28, CLK_PLL_PERIPH0, 29);

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