| /bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| A D | startup_psoc6_01_cm0plus.s | 59 DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0
60 DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1
61 DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2
62 DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3
63 DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4
64 DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5
65 DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6
66 DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7
67 DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8
68 DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9
[all …]
|
| A D | linker.sct | 48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
61 ; The size of the stack section at the end of CM0+ SRAM
|
| /bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/libs/TARGET_CY8CKIT-062-WIFI-BT/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| A D | startup_psoc6_01_cm0plus.s | 59 DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0
60 DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1
61 DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2
62 DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3
63 DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4
64 DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5
65 DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6
66 DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7
67 DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8
68 DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9
[all …]
|
| /bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM0P/TOOLCHAIN_IAR/ |
| A D | startup_psoc6_01_cm0plus.s | 83 DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0
84 DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1
85 DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2
86 DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3
87 DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4
88 DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5
89 DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6
90 DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7
91 DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8
92 DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9
[all …]
|
| /bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/libs/TARGET_CY8CKIT-062-WIFI-BT/COMPONENT_CM0P/TOOLCHAIN_IAR/ |
| A D | startup_psoc6_01_cm0plus.s | 83 DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0
84 DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1
85 DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2
86 DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3
87 DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4
88 DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5
89 DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6
90 DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7
91 DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8
92 DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9
[all …]
|
| /bsp/m16c62p/drivers/ |
| A D | bsp.c | 43 …CM0.BYTE &= ~0x40; /* Set divide ratio to 1 … in mcu_init()
|
| /bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/libs/TARGET_CY8CKIT-062-WIFI-BT/ |
| A D | RELEASE.md | 12 * CM0+ Linker script & startup code for GCC, IAR, and ARM toolchains
20 * PSoC 64 boards: Fix cybsp_init not recognizing that a prebuilt CM0+ image is in use when using TF…
73 * Updated linker scripts and startup code for the CM0+ and CM4 cores. The files are now in core spe…
|
| /bsp/Infineon/psoc6-cy8ckit-062s4/libs/TARGET_CY8CKIT-062S4/ |
| A D | RELEASE.md | 12 * CM0+ Linker script & startup code for GCC, IAR, and ARM toolchains
20 * PSoC 64 boards: Fix cybsp_init not recognizing that a prebuilt CM0+ image is in use when using TF…
73 * Updated linker scripts and startup code for the CM0+ and CM4 cores. The files are now in core spe…
|
| /bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/ |
| A D | RELEASE.md | 12 * CM0+ Linker script & startup code for GCC, IAR, and ARM toolchains
20 * PSoC 64 boards: Fix cybsp_init not recognizing that a prebuilt CM0+ image is in use when using TF…
73 * Updated linker scripts and startup code for the CM0+ and CM4 cores. The files are now in core spe…
|
| /bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/ |
| A D | RELEASE.md | 12 * CM0+ Linker script & startup code for GCC, IAR, and ARM toolchains
24 * PSoC 64 boards: Fix cybsp_init not recognizing that a prebuilt CM0+ image is in use when using TF…
77 * Updated linker scripts and startup code for the CM0+ and CM4 cores. The files are now in core spe…
|
| /bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/ |
| A D | RELEASE.md | 12 * CM0+ Linker script & startup code for GCC, IAR, and ARM toolchains
20 * PSoC 64 boards: Fix cybsp_init not recognizing that a prebuilt CM0+ image is in use when using TF…
73 * Updated linker scripts and startup code for the CM0+ and CM4 cores. The files are now in core spe…
|
| /bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/ |
| A D | RELEASE.md | 12 * CM0+ Linker script & startup code for GCC, IAR, and ARM toolchains
20 * PSoC 64 boards: Fix cybsp_init not recognizing that a prebuilt CM0+ image is in use when using TF…
73 * Updated linker scripts and startup code for the CM0+ and CM4 cores. The files are now in core spe…
|
| /bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/ |
| A D | RELEASE.md | 12 * CM0+ Linker script & startup code for GCC, IAR, and ARM toolchains
20 * PSoC 64 boards: Fix cybsp_init not recognizing that a prebuilt CM0+ image is in use when using TF…
73 * Updated linker scripts and startup code for the CM0+ and CM4 cores. The files are now in core spe…
|
| /bsp/Infineon/psoc6-cy8ckit-062s4/board/linker_scripts/ |
| A D | link.sct | 52 ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
65 ; More about CM0+ prebuilt images, see here:
|
| /bsp/Infineon/psoc6-cy8ckit-062s4/libs/TARGET_CY8CKIT-062S4/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| A D | linker.sct | 48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
61 ; The size of the stack section at the end of CM0+ SRAM
|
| /bsp/Infineon/psoc6-cy8ckit-062s4/libs/TARGET_CY8CKIT-062S4/COMPONENT_CM4/TOOLCHAIN_ARM/ |
| A D | linker.sct | 52 ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
65 ; More about CM0+ prebuilt images, see here:
|
| /bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/ |
| A D | link.sct | 52 ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
65 ; More about CM0+ prebuilt images, see here:
|
| /bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| A D | linker.sct | 48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
61 ; The size of the stack section at the end of CM0+ SRAM
|
| /bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/ |
| A D | linker.sct | 52 ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
65 ; More about CM0+ prebuilt images, see here:
|
| /bsp/Infineon/psoc6-evaluationkit-062S2/board/linker_scripts/ |
| A D | link.sct | 52 ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
65 ; More about CM0+ prebuilt images, see here:
|
| /bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| A D | linker.sct | 48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
61 ; The size of the stack section at the end of CM0+ SRAM
|
| /bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_CM4/TOOLCHAIN_ARM/ |
| A D | linker.sct | 52 ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
65 ; More about CM0+ prebuilt images, see here:
|
| /bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| A D | linker.sct | 48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
61 ; The size of the stack section at the end of CM0+ SRAM
|
| /bsp/Infineon/psoc6-cy8ckit-062-BLE/board/linker_scripts/ |
| A D | link.sct | 52 ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
65 ; More about CM0+ prebuilt images, see here:
|
| /bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/TOOLCHAIN_ARM/ |
| A D | linker.sct | 54 ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
67 ; More about CM0+ prebuilt images, see here:
|