1 /* 2 * Copyright (C) 2019 ETH Zurich, University of Bologna 3 * and GreenWaves Technologies 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 #ifndef HAL_INCLUDE_HAL_UDMA_CORE_PERIPH_H_ 19 #define HAL_INCLUDE_HAL_UDMA_CORE_PERIPH_H_ 20 21 #include <stdint.h> 22 23 /* ---------------------------------------------------------------------------- 24 -- UDMA_CORE Peripheral Access Layer -- 25 ---------------------------------------------------------------------------- */ 26 27 /** UDMA_CORE_Type Register Layout Typedef */ 28 /* TODO: refactor this really not good code */ 29 typedef struct 30 { 31 volatile uint32_t saddr; /**< RX/TX/CMD Channel uDMA transfer address of associated buffer */ 32 volatile uint32_t size; /**< RX/TX/CMD Channel uDMA transfer size of buffer */ 33 volatile uint32_t cfg; /**< RX/TX/CMD Channel uDMA transfer configuration */ 34 volatile uint32_t initcfg; /**< Not used. */ 35 } udma_channel_t; 36 37 38 typedef enum 39 { 40 RX_CHANNEL = 0, 41 TX_CHANNEL = 1, 42 COMMAND_CHANNEL = 2 43 } udma_channel_e; 44 45 /* ---------------------------------------------------------------------------- 46 -- UDMA_CORE Register Bitfield Access -- 47 ---------------------------------------------------------------------------- */ 48 49 /*! @name RX_SADDR */ 50 /* Configure pointer to memory buffer: 51 - Read: value of the pointer until transfer is over. Else returns 0 52 - Write: set Address Pointer to memory buffer start address */ 53 #define UDMA_CORE_RX_SADDR_RX_SADDR_MASK (0x1fffff) 54 #define UDMA_CORE_RX_SADDR_RX_SADDR_SHIFT (0) 55 #define UDMA_CORE_RX_SADDR_RX_SADDR(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_SADDR_RX_SADDR_SHIFT)) & UDMA_CORE_RX_SADDR_RX_SADDR_MASK) 56 57 /* Reserved/Not used. */ 58 #define UDMA_CORE_RX_SADDR_RESERVED_0_MASK (0xffe00000) 59 #define UDMA_CORE_RX_SADDR_RESERVED_0_SHIFT (21) 60 #define UDMA_CORE_RX_SADDR_RESERVED_0(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_SADDR_RESERVED_0_SHIFT)) & UDMA_CORE_RX_SADDR_RESERVED_0_MASK) 61 62 63 /*! @name RX_SIZE */ 64 /* Buffer size in byte. (128kBytes maximum) 65 - Read: buffer size left 66 - Write: set buffer size */ 67 #define UDMA_CORE_RX_SIZE_RX_SIZE_MASK (0xfffff) 68 #define UDMA_CORE_RX_SIZE_RX_SIZE_SHIFT (0) 69 #define UDMA_CORE_RX_SIZE_RX_SIZE(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_SIZE_RX_SIZE_SHIFT)) & UDMA_CORE_RX_SIZE_RX_SIZE_MASK) 70 71 /* Reserved/Not used. */ 72 #define UDMA_CORE_RX_SIZE_RESERVED_0_MASK (0xfff00000) 73 #define UDMA_CORE_RX_SIZE_RESERVED_0_SHIFT (20) 74 #define UDMA_CORE_RX_SIZE_RESERVED_0(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_SIZE_RESERVED_0_SHIFT)) & UDMA_CORE_RX_SIZE_RESERVED_0_MASK) 75 76 77 /*! @name RX_CFG */ 78 /* Channel continuous mode: 79 - 1'b0: disable 80 - 1'b1: enable 81 At the end of the buffer the uDMA reloads the address and size and starts a new transfer. */ 82 #define UDMA_CORE_RX_CFG_CONTINOUS_MASK (0x1) 83 #define UDMA_CORE_RX_CFG_CONTINOUS_SHIFT (0) 84 #define UDMA_CORE_RX_CFG_CONTINOUS(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_CFG_CONTINOUS_SHIFT)) & UDMA_CORE_RX_CFG_CONTINOUS_MASK) 85 86 /* Channel transfer size used to increment uDMA buffer address pointer: 87 - 2'b00: +1 (8 bits) 88 - 2'b01: +2 (16 bits) 89 - 2'b10: +4 (32 bits) 90 - 2'b11: +0 */ 91 #define UDMA_CORE_RX_CFG_DATASIZE_MASK (0x6) 92 #define UDMA_CORE_RX_CFG_DATASIZE_SHIFT (1) 93 #define UDMA_CORE_RX_CFG_DATASIZE(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_CFG_DATASIZE_SHIFT)) & UDMA_CORE_RX_CFG_DATASIZE_MASK) 94 95 /* Reserved/Not used. */ 96 #define UDMA_CORE_RX_CFG_RESERVED_0_MASK (0x8) 97 #define UDMA_CORE_RX_CFG_RESERVED_0_SHIFT (3) 98 #define UDMA_CORE_RX_CFG_RESERVED_0(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_CFG_RESERVED_0_SHIFT)) & UDMA_CORE_RX_CFG_RESERVED_0_MASK) 99 100 /* Channel enable and start transfer: 101 - 1'b0: disable 102 - 1'b1: enable 103 This signal is used also to queue a transfer if one is already ongoing. */ 104 #define UDMA_CORE_RX_CFG_EN_MASK (0x10) 105 #define UDMA_CORE_RX_CFG_EN_SHIFT (4) 106 #define UDMA_CORE_RX_CFG_EN(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_CFG_EN_SHIFT)) & UDMA_CORE_RX_CFG_EN_MASK) 107 108 /* Transfer pending in queue status flag: 109 - 1'b0: no pending transfer in the queue 110 - 1'b1: pending transfer in the queue */ 111 #define UDMA_CORE_RX_CFG_PENDING_MASK (0x20) 112 #define UDMA_CORE_RX_CFG_PENDING_SHIFT (5) 113 #define UDMA_CORE_RX_CFG_PENDING(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_CFG_PENDING_SHIFT)) & UDMA_CORE_RX_CFG_PENDING_MASK) 114 115 /* Channel clear and stop transfer: 116 - 1'b0: disable 117 - 1'b1: stop and clear the on-going transfer */ 118 #define UDMA_CORE_RX_CFG_CLR_MASK (0x40) 119 #define UDMA_CORE_RX_CFG_CLR_SHIFT (6) 120 #define UDMA_CORE_RX_CFG_CLR(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_CFG_CLR_SHIFT)) & UDMA_CORE_RX_CFG_CLR_MASK) 121 122 /* Reserved/Not used. */ 123 #define UDMA_CORE_RX_CFG_RESERVED_1_MASK (0xffffff80) 124 #define UDMA_CORE_RX_CFG_RESERVED_1_SHIFT (7) 125 #define UDMA_CORE_RX_CFG_RESERVED_1(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_CFG_RESERVED_1_SHIFT)) & UDMA_CORE_RX_CFG_RESERVED_1_MASK) 126 127 128 /*! @name RX_INITCFG */ 129 /* Reserved/Not used. */ 130 #define UDMA_CORE_RX_INITCFG_RESERVED_0_MASK (0xffffffff) 131 #define UDMA_CORE_RX_INITCFG_RESERVED_0_SHIFT (0) 132 #define UDMA_CORE_RX_INITCFG_RESERVED_0(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_INITCFG_RESERVED_0_SHIFT)) & UDMA_CORE_RX_INITCFG_RESERVED_0_MASK) 133 134 135 /*! @name TX_SADDR */ 136 /* Configure pointer to memory buffer: 137 - Read: value of the pointer until transfer is over. Else returns 0 138 - Write: set Address Pointer to memory buffer start address */ 139 #define UDMA_CORE_TX_SADDR_TX_SADDR_MASK (0x1fffff) 140 #define UDMA_CORE_TX_SADDR_TX_SADDR_SHIFT (0) 141 #define UDMA_CORE_TX_SADDR_TX_SADDR(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_SADDR_TX_SADDR_SHIFT)) & UDMA_CORE_TX_SADDR_TX_SADDR_MASK) 142 143 /* Reserved/Not used. */ 144 #define UDMA_CORE_TX_SADDR_RESERVED_0_MASK (0xffe00000) 145 #define UDMA_CORE_TX_SADDR_RESERVED_0_SHIFT (21) 146 #define UDMA_CORE_TX_SADDR_RESERVED_0(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_SADDR_RESERVED_0_SHIFT)) & UDMA_CORE_TX_SADDR_RESERVED_0_MASK) 147 148 149 /*! @name TX_SIZE */ 150 /* Buffer size in byte. (128kBytes maximum) 151 - Read: buffer size left 152 - Write: set buffer size */ 153 #define UDMA_CORE_TX_SIZE_TX_SIZE_MASK (0xfffff) 154 #define UDMA_CORE_TX_SIZE_TX_SIZE_SHIFT (0) 155 #define UDMA_CORE_TX_SIZE_TX_SIZE(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_SIZE_TX_SIZE_SHIFT)) & UDMA_CORE_TX_SIZE_TX_SIZE_MASK) 156 157 /* Reserved/Not used. */ 158 #define UDMA_CORE_TX_SIZE_RESERVED_0_MASK (0xfff00000) 159 #define UDMA_CORE_TX_SIZE_RESERVED_0_SHIFT (20) 160 #define UDMA_CORE_TX_SIZE_RESERVED_0(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_SIZE_RESERVED_0_SHIFT)) & UDMA_CORE_TX_SIZE_RESERVED_0_MASK) 161 162 163 /*! @name TX_CFG */ 164 /* Channel continuous mode: 165 - 1'b0: disable 166 - 1'b1: enable 167 At the end of the buffer the uDMA reloads the address and size and starts a new transfer. */ 168 #define UDMA_CORE_TX_CFG_CONTINOUS_MASK (0x1) 169 #define UDMA_CORE_TX_CFG_CONTINOUS_SHIFT (0) 170 #define UDMA_CORE_TX_CFG_CONTINOUS(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_CFG_CONTINOUS_SHIFT)) & UDMA_CORE_TX_CFG_CONTINOUS_MASK) 171 172 /* Channel transfer size used to increment uDMA buffer address pointer: 173 - 2'b00: +1 (8 bits) 174 - 2'b01: +2 (16 bits) 175 - 2'b10: +4 (32 bits) 176 - 2'b11: +0 */ 177 #define UDMA_CORE_TX_CFG_DATASIZE_MASK (0x6) 178 #define UDMA_CORE_TX_CFG_DATASIZE_SHIFT (1) 179 #define UDMA_CORE_TX_CFG_DATASIZE(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_CFG_DATASIZE_SHIFT)) & UDMA_CORE_TX_CFG_DATASIZE_MASK) 180 181 /* Reserved/Not used. */ 182 #define UDMA_CORE_TX_CFG_RESERVED_0_MASK (0x8) 183 #define UDMA_CORE_TX_CFG_RESERVED_0_SHIFT (3) 184 #define UDMA_CORE_TX_CFG_RESERVED_0(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_CFG_RESERVED_0_SHIFT)) & UDMA_CORE_TX_CFG_RESERVED_0_MASK) 185 186 /* Channel enable and start transfer: 187 - 1'b0: disable 188 - 1'b1: enable 189 This signal is used also to queue a transfer if one is already ongoing. */ 190 #define UDMA_CORE_TX_CFG_EN_MASK (0x10) 191 #define UDMA_CORE_TX_CFG_EN_SHIFT (4) 192 #define UDMA_CORE_TX_CFG_EN(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_CFG_EN_SHIFT)) & UDMA_CORE_TX_CFG_EN_MASK) 193 194 /* Transfer pending in queue status flag: 195 - 1'b0: no pending transfer in the queue 196 - 1'b1: pending transfer in the queue */ 197 #define UDMA_CORE_TX_CFG_PENDING_MASK (0x20) 198 #define UDMA_CORE_TX_CFG_PENDING_SHIFT (5) 199 #define UDMA_CORE_TX_CFG_PENDING(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_CFG_PENDING_SHIFT)) & UDMA_CORE_TX_CFG_PENDING_MASK) 200 201 /* Channel clear and stop transfer: 202 - 1'b0: disable 203 - 1'b1: stop and clear the on-going transfer */ 204 #define UDMA_CORE_TX_CFG_CLR_MASK (0x40) 205 #define UDMA_CORE_TX_CFG_CLR_SHIFT (6) 206 #define UDMA_CORE_TX_CFG_CLR(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_CFG_CLR_SHIFT)) & UDMA_CORE_TX_CFG_CLR_MASK) 207 208 /* Reserved/Not used. */ 209 #define UDMA_CORE_TX_CFG_RESERVED_1_MASK (0xffffff80) 210 #define UDMA_CORE_TX_CFG_RESERVED_1_SHIFT (7) 211 #define UDMA_CORE_TX_CFG_RESERVED_1(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_CFG_RESERVED_1_SHIFT)) & UDMA_CORE_TX_CFG_RESERVED_1_MASK) 212 213 214 /*! @name TX_INITCFG */ 215 /* Reserved/Not used. */ 216 #define UDMA_CORE_TX_INITCFG_RESERVED_0_MASK (0xffffffff) 217 #define UDMA_CORE_TX_INITCFG_RESERVED_0_SHIFT (0) 218 #define UDMA_CORE_TX_INITCFG_RESERVED_0(val) (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_INITCFG_RESERVED_0_SHIFT)) & UDMA_CORE_TX_INITCFG_RESERVED_0_MASK) 219 220 221 222 223 /*! @name RX_SADDR */ 224 typedef union 225 { 226 struct 227 { 228 /* Configure pointer to memory buffer: 229 - Read: value of the pointer until transfer is over. Else returns 0 230 - Write: set Address Pointer to memory buffer start address */ 231 uint32_t rx_saddr:21; 232 /* Reserved/Not used. */ 233 uint32_t reserved_0:11; 234 } field; 235 uint32_t word; 236 } udma_core_rx_saddr_t; 237 238 /*! @name RX_SIZE */ 239 typedef union 240 { 241 struct 242 { 243 /* Buffer size in byte. (128kBytes maximum) 244 - Read: buffer size left 245 - Write: set buffer size */ 246 uint32_t rx_size:20; 247 /* Reserved/Not used. */ 248 uint32_t reserved_0:12; 249 } field; 250 uint32_t word; 251 } udma_core_rx_size_t; 252 253 /*! @name RX_CFG */ 254 typedef union 255 { 256 struct 257 { 258 /* Channel continuous mode: 259 - 1'b0: disable 260 - 1'b1: enable 261 At the end of the buffer the uDMA reloads the address and size and starts a new transfer. */ 262 uint32_t continous:1; 263 /* Channel transfer size used to increment uDMA buffer address pointer: 264 - 2'b00: +1 (8 bits) 265 - 2'b01: +2 (16 bits) 266 - 2'b10: +4 (32 bits) 267 - 2'b11: +0 */ 268 uint32_t datasize:2; 269 /* Reserved/Not used. */ 270 uint32_t reserved_0:1; 271 /* Channel enable and start transfer: 272 - 1'b0: disable 273 - 1'b1: enable 274 This signal is used also to queue a transfer if one is already ongoing. */ 275 uint32_t en:1; 276 /* Transfer pending in queue status flag: 277 - 1'b0: no pending transfer in the queue 278 - 1'b1: pending transfer in the queue */ 279 uint32_t pending:1; 280 /* Channel clear and stop transfer: 281 - 1'b0: disable 282 - 1'b1: stop and clear the on-going transfer */ 283 uint32_t clr:1; 284 /* Reserved/Not used. */ 285 uint32_t reserved_1:25; 286 } field; 287 uint32_t word; 288 } udma_core_rx_cfg_t; 289 290 /*! @name RX_INITCFG */ 291 typedef union 292 { 293 struct 294 { 295 /* Reserved/Not used. */ 296 uint32_t reserved_0:32; 297 } field; 298 uint32_t word; 299 } udma_core_rx_initcfg_t; 300 301 /*! @name TX_SADDR */ 302 typedef union 303 { 304 struct 305 { 306 /* Configure pointer to memory buffer: 307 - Read: value of the pointer until transfer is over. Else returns 0 308 - Write: set Address Pointer to memory buffer start address */ 309 uint32_t tx_saddr:21; 310 /* Reserved/Not used. */ 311 uint32_t reserved_0:11; 312 } field; 313 uint32_t word; 314 } udma_core_tx_saddr_t; 315 316 /*! @name TX_SIZE */ 317 typedef union 318 { 319 struct 320 { 321 /* Buffer size in byte. (128kBytes maximum) 322 - Read: buffer size left 323 - Write: set buffer size */ 324 uint32_t tx_size:20; 325 /* Reserved/Not used. */ 326 uint32_t reserved_0:12; 327 } field; 328 uint32_t word; 329 } udma_core_tx_size_t; 330 331 /*! @name TX_CFG */ 332 typedef union 333 { 334 struct 335 { 336 /* Channel continuous mode: 337 - 1'b0: disable 338 - 1'b1: enable 339 At the end of the buffer the uDMA reloads the address and size and starts a new transfer. */ 340 uint32_t continous:1; 341 /* Channel transfer size used to increment uDMA buffer address pointer: 342 - 2'b00: +1 (8 bits) 343 - 2'b01: +2 (16 bits) 344 - 2'b10: +4 (32 bits) 345 - 2'b11: +0 */ 346 uint32_t datasize:2; 347 /* Reserved/Not used. */ 348 uint32_t reserved_0:1; 349 /* Channel enable and start transfer: 350 - 1'b0: disable 351 - 1'b1: enable 352 This signal is used also to queue a transfer if one is already ongoing. */ 353 uint32_t en:1; 354 /* Transfer pending in queue status flag: 355 - 1'b0: no pending transfer in the queue 356 - 1'b1: pending transfer in the queue */ 357 uint32_t pending:1; 358 /* Channel clear and stop transfer: 359 - 1'b0: disable 360 - 1'b1: stop and clear the on-going transfer */ 361 uint32_t clr:1; 362 /* Reserved/Not used. */ 363 uint32_t reserved_1:25; 364 } field; 365 uint32_t word; 366 } udma_core_tx_cfg_t; 367 368 /*! @name TX_INITCFG */ 369 typedef union 370 { 371 struct 372 { 373 /* Reserved/Not used. */ 374 uint32_t reserved_0:32; 375 } field; 376 uint32_t word; 377 } udma_core_tx_initcfg_t; 378 379 380 #define UDMA_CORE_CFG_DATASIZE_8 (0x0) 381 #define UDMA_CORE_CFG_DATASIZE_16 (0x1) 382 #define UDMA_CORE_CFG_DATASIZE_32 (0x2) 383 384 #endif /* HAL_INCLUDE_HAL_UDMA_CORE_PERIPH_H_ */ 385