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Searched refs:CONF_GCLK_ADC0_SRC (Results 1 – 4 of 4) sorted by relevance

/bsp/microchip/samc21/bsp/config/
A Dperipheral_clk_config.h27 #ifndef CONF_GCLK_ADC0_SRC
28 #define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val macro
/bsp/microchip/same54/bsp/config/
A Dperipheral_clk_config.h35 #ifndef CONF_GCLK_ADC0_SRC
36 #define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val macro
/bsp/microchip/samc21/bsp/
A Ddriver_init.c42 hri_gclk_write_PCHCTRL_reg(GCLK, ADC0_GCLK_ID, CONF_GCLK_ADC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); in ADC_0_CLOCK_init()
/bsp/microchip/same54/bsp/
A Ddriver_init.c43 hri_gclk_write_PCHCTRL_reg(GCLK, ADC0_GCLK_ID, CONF_GCLK_ADC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); in ADC_0_CLOCK_init()

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