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Searched refs:CONF_GCLK_SERCOM0_SLOW_SRC (Results 1 – 4 of 4) sorted by relevance

/bsp/microchip/saml10/bsp/config/
A Dperipheral_clk_config.h73 #ifndef CONF_GCLK_SERCOM0_SLOW_SRC
74 #define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK1_Val macro
/bsp/microchip/samc21/bsp/config/
A Dperipheral_clk_config.h91 #ifndef CONF_GCLK_SERCOM0_SLOW_SRC
92 #define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK1_Val macro
/bsp/microchip/saml10/bsp/
A Ddriver_init.c76 …hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCH… in I2C_0_CLOCK_init()
/bsp/microchip/samc21/bsp/
A Ddriver_init.c91 …hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCH… in I2C_0_CLOCK_init()

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